Meghraj Kachare - Academia.edu (original) (raw)

Papers by Meghraj Kachare

Conference Record of the Twenty-Ninth IEEE Photovoltaic Specialists Conference, 2002.

Electronics Letters, 2003

A new analogue switch suitable for operation at very low-voltage supply in a standard CMOS techno... more A new analogue switch suitable for operation at very low-voltage supply in a standard CMOS technology is presented. The proposed switch is based on ‘quasi-floating-gate’ transistors and has a simple and compact structure. For illustrative purposes, two sample-and-hold circuits operating from a single supply voltage close to the threshold voltage of a transistor, and using the proposed technique, are presented. Experimental results obtained from prototypes in a 1.5 µm CMOS technology are provided.

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

ABSTRACT

IEEE Transactions on Circuits and Systems I-regular Papers, 2005

A versatile low-voltage CMOS circuit with a triangular/trapezoidal transconductance characteristi... more A versatile low-voltage CMOS circuit with a triangular/trapezoidal transconductance characteristic and independently programmable slope (keeping constant height or constant width), height (keeping constant slope or constant width), and horizontal position is presented. Simulation results using Cadence DFW-II that verify the functionality of the circuit with ±1.5-V supplies are presented. A chip prototype has been fabricated in a 0.5-μm technology and

IEEE Transactions on Circuits and Systems II: Express Briefs, 2000

A novel CMOS linear transconductor is presented. The use of simple and accurate voltage buffers t... more A novel CMOS linear transconductor is presented. The use of simple and accurate voltage buffers to drive two MOS transistors operating in the triode region leads to a highly linear voltage-to-current conversion. Transconductance gain can be continuously and precisely adjusted using dc level shifters. Measurement results of a balanced transconductor fabricated in a 0.5-m CMOS technology show a total harmonic distortion of 54 dB at 100 kHz for an 80-A peak-to-peak output, using a supply voltage of 2 V. It requires 0.07-mm 2 of silicon area and features 0.96 mW of static power consumption.

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03., 2003

A simple scheme to boost the supply voltage above and below the supply rails is introduced. Three... more A simple scheme to boost the supply voltage above and below the supply rails is introduced. Three applications of this technique are discussed: a) a rail-to-rail sample and hold circuit operating from a single supply voltage close to a transistor's threshold voltage; b) a low-voltage rail-to-rail switch for high precision applications; c) a NAND gate capable of operating with a

Conference Record of the Twenty-Ninth IEEE Photovoltaic Specialists Conference, 2002.

Electronics Letters, 2003

A new analogue switch suitable for operation at very low-voltage supply in a standard CMOS techno... more A new analogue switch suitable for operation at very low-voltage supply in a standard CMOS technology is presented. The proposed switch is based on ‘quasi-floating-gate’ transistors and has a simple and compact structure. For illustrative purposes, two sample-and-hold circuits operating from a single supply voltage close to the threshold voltage of a transistor, and using the proposed technique, are presented. Experimental results obtained from prototypes in a 1.5 µm CMOS technology are provided.

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

ABSTRACT

IEEE Transactions on Circuits and Systems I-regular Papers, 2005

A versatile low-voltage CMOS circuit with a triangular/trapezoidal transconductance characteristi... more A versatile low-voltage CMOS circuit with a triangular/trapezoidal transconductance characteristic and independently programmable slope (keeping constant height or constant width), height (keeping constant slope or constant width), and horizontal position is presented. Simulation results using Cadence DFW-II that verify the functionality of the circuit with ±1.5-V supplies are presented. A chip prototype has been fabricated in a 0.5-μm technology and

IEEE Transactions on Circuits and Systems II: Express Briefs, 2000

A novel CMOS linear transconductor is presented. The use of simple and accurate voltage buffers t... more A novel CMOS linear transconductor is presented. The use of simple and accurate voltage buffers to drive two MOS transistors operating in the triode region leads to a highly linear voltage-to-current conversion. Transconductance gain can be continuously and precisely adjusted using dc level shifters. Measurement results of a balanced transconductor fabricated in a 0.5-m CMOS technology show a total harmonic distortion of 54 dB at 100 kHz for an 80-A peak-to-peak output, using a supply voltage of 2 V. It requires 0.07-mm 2 of silicon area and features 0.96 mW of static power consumption.

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03., 2003

A simple scheme to boost the supply voltage above and below the supply rails is introduced. Three... more A simple scheme to boost the supply voltage above and below the supply rails is introduced. Three applications of this technique are discussed: a) a rail-to-rail sample and hold circuit operating from a single supply voltage close to a transistor's threshold voltage; b) a low-voltage rail-to-rail switch for high precision applications; c) a NAND gate capable of operating with a