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Papers by Mohamed Elbeshti

Research paper thumbnail of Design of a Scalable Network Interface to Support Enhanced TCP and UDP Processing for High Speed Networks

Communication networks have advanced rapidly in providing additional services, with improvements ... more Communication networks have advanced rapidly in providing additional services, with improvements made to their bandwidth and the integration of advanced technology. As the speed of networks exceeds 10 Gbps, the time frame for completing the processing of TCP and UDP packets has become extremely short. The design and implementation of high performance Network Interfaces (NIs) that can support offload protocol functions for current and next-generation networksis challenging. In this thesis two software approaches are presented to enhance protocol processing of TCP and UDP in the network interface. A novel software Large Receive Offload (LRO) approach for enhancing the receiving side has been proposed.The LRO works by aggregating the incoming TCP and UDP packets into larger packets inside the NI's buffer. The receiving side software has been improved to support out-of-order packets. The second proposed software solution is applied on the Large Send Offload (LSO). The proposed LSO function processing is implemented by segmenting TCP and UDP messages that are larger than the Maximum Transmission Unit to the Maximum Segment Size. New packet headers are generatedfor each new outgoing packet. A scalable programmable NI based 32-bit RISC core is presented that can support 100 Gbps network speeds. Acceleration of the processing time frame required at the NI has been implemented to prevent hazards (such as Data Hazard and Control Hazard) during the execution of the LRO and the LSO functions. An R2000/3000 RISC has been used in order to test the LRO and LSO functions and to discover the instruction set that is most suitable. Following this the VHDL NI was implemented with three pipeline RISC cores, a simple DMA controller and Content Addressable Memory. An evaluation of the desired RISC clock rate that is required to process TCP and UDP streams at 100 Gbps was conducted. It was determined that aRISC core running at 752 MHz with a DMA clock of 3753 MHz was able to process packets 512 bytes or larger fast enough to support 100 Gbps network speeds.

Research paper thumbnail of A RISC-based ATM network interface: processing, architecture, scalability and performance

Research paper thumbnail of Large Sending Offload: Design and Implementation for High-Speed Communications Rate Up to 100 GBPS

International journal of new computer architectures and their applications, 2013

With the release of P802.3ba IEEE, send and receive data at 40 Gbps to 100 Gbps could become poss... more With the release of P802.3ba IEEE, send and receive data at 40 Gbps to 100 Gbps could become possible. Offloading part of the processing protocol to the network card showed success in sending data at high speeds up to 10 Gbps. Eventually, by enhancing transmission processing and taking advantage of the high speed, a potential network interface structure and performance needs to be addressed and implemented in order to send packets quickly corresponding with 40 Gbps and 100 Gbps. In this paper, such a network interface that supports high speeds after 10 Gbps has been designed. An alternative Large Sending Offload algorithm for sending TCP/IP and UDP/IP packets has also been implemented. A cost-effective RISC processor and a simple DMA for data transfer have also been implemented and simulated and tested for high speed. The behavior model shows that, a 450 MHz RISC core can support the sending-side processing up to 100 Gbps transmission speed for the TCP/IP and UDP/IP protocol when the MTU is 512 bytes or larger. A DMA with 2115 MHz is required to eliminate the idle cycles while transferring data over the 64-bit local bus.

Research paper thumbnail of Science Education in Libya

Science Education in Countries Along the Belt & Road, 2022

This chapter provides a brief introduction to the geographical location of Libya, its population ... more This chapter provides a brief introduction to the geographical location of Libya, its population and the current political system. We highlight the levels of the education system in Libya (primary, basic and higher education). This includes the number of enrolled students and the number of dropout rates per year. Training and development in some schools and universities that have established eLearning and emerging technologies to enhance science education teaching or learning are discussed. The assessment methodology is also considered. The chapter also provides some statistics about the economic situation technologies and cultural development in Libya. Challenges, strategies, reflections, issues, and future paths form the latter part of this chapter.

Research paper thumbnail of A RISC-based ATM network interface: processing, architecture, scalability and performance

Research paper thumbnail of Design a scalable ethernet Network Interface supporting the Large Receive Offload

2012 International Symposium on Communications and Information Technologies (ISCIT), 2012

The Ethernet speed has increased to 40-100 Gbps since the release of IEEE P802.3ba. In this paper... more The Ethernet speed has increased to 40-100 Gbps since the release of IEEE P802.3ba. In this paper, we have enhanced the Intel's Large Receive Offload Linux software driver function to manage the out-of-order packets and designed a scalable Network Interface based RISC core to support this function in the Network Interface. The RISC's performance and data movements for high communication rates up to 100 Gbps have been measured, and the results presented herein show that a cost-effective embedded RISC core can provide the required efficiency of the network interface to support a wide range of transmission line speeds, up to 100 Gbps. Furthermore, we have found several techniques that can contribute to packet processing and work with fewer headers and less data copying in a host memory.

Research paper thumbnail of An Evaluation of TCP and UDP Protocols Processing Required for Network Interface Design at 100 Gbps

2011 IEEE International Conference on High Performance Computing and Communications, 2011

Today major challenges are faced by server platforms while performing TCP/IP or UDP/IP protocol p... more Today major challenges are faced by server platforms while performing TCP/IP or UDP/IP protocol processing. For instance, the speed of networks now exceeds the gigabit per sec Gbps, the design and implementations of high-performance Network Interfaces (NI) have become very challenging. There are different possible design approaches to implement high-speed NI. However, using the General Purpose Processing (GPP) as a core engine to offload some, if not all, of the TCP/IP or UDP/IP protocol functions can deliver some important features to NIs, such as simplicity, scalability, shorter developing cycle time and reduced costs. Still it is not clear whether the GPP can provide the processing required for high-speed line over 10 Gbps. Also, where is the limit of such GPP in supporting the processing of network interfaces? In this paper, we have measured the amount of processing required for Ethernet Network Interfaces (ENI) design supporting different transmission line speeds. A NIprogrammable based RISC model has been designed to measure the processing required for the ENI|. The results have shown that a RISC core running at 240 MHz can be used as a processing core in high-speed ENI. Such core can support a wide range of transmission line speeds, up to 100 Gbps. Also, we have discussed some of the design issues that are related to RISC core based NI and the data movement type.

Research paper thumbnail of TCP and UDP processing requirements for network interface design at 100 Gbps

Today major challenges are faced by server platforms while processing TCP/IP or UDP/IP. For insta... more Today major challenges are faced by server platforms while processing TCP/IP or UDP/IP. For instance, the speed of networks now exceeds the gigabit per sec Gbps, the design and implementations of high-performance Network Interfaces (NI) have become very challenging. There are different possible design approaches to implement high-speed NI. However, using the General Purpose Processor (GPP) as a core engine to offload some, if not all, of the TCP/IP or UDP/IP protocol functions can deliver some important features to NIs, such as simplicity, scalability, shorter development cycle time and reduced costs. Still it is not clear whether the GPP can provide the processing required Ethernet beyond 10 Gbps. Also, what is the limit of such GPP in supporting the processing of network interfaces? In this paper, we have measured the amount of processing required for Ethernet Network Interfaces (ENI) supporting different transmission line speeds. A NI-programmable based RISC model has been designed to measure the processing required for the ENI. The results have shown that a RISC core running at 240 MHz can be used as a processing core in high-speed ENI. Such core can support a wide range of transmission line speeds, up to 100 Gbps. Also, we have discussed some of the design issues that are related to RISC core based NI and the data movement type.

Research paper thumbnail of Design and Simulating a Specialized Embedded Cores for UDP Network Interface Processing

Modelling and Simulation / 804: Signal and Image Processing, 2013

The speed of Ethernet networks has increased to 40-100 Gbps since the release of IEEE P802.3ba. E... more The speed of Ethernet networks has increased to 40-100 Gbps since the release of IEEE P802.3ba. Enhancing the protocol processing at the end node is essential to meet the demands of the increased network speeds. This research presents an enhanced pre-packet processing for inbound and outbound processing using a scalable Network Interface-based three-pipeline Embedded Processor. The designed Network Interfaces uses a specialized cost-effective 760 MHz embedded processor core can support a wide range of received UDP/IP packets, up to 100 Gbps. A 430 MHz Embedded Processor can be used for the send side. Furthermore, we have provided a processing methodology for Large Receive Offload and Large Send Offload that can contribute to pre-packet processing and work with fewer headers and data transfer from the network interface.

Research paper thumbnail of Design of a Scalable Network Interface to Support Enhanced TCP and UDP Processing for High Speed Networks

Communication networks have advanced rapidly in providing additional services, with improvements ... more Communication networks have advanced rapidly in providing additional services, with improvements made to their bandwidth and the integration of advanced technology. As the speed of networks exceeds 10 Gbps, the time frame for completing the processing of TCP and UDP packets has become extremely short. The design and implementation of high performance Network Interfaces (NIs) that can support offload protocol functions for current and next-generation networksis challenging. In this thesis two software approaches are presented to enhance protocol processing of TCP and UDP in the network interface. A novel software Large Receive Offload (LRO) approach for enhancing the receiving side has been proposed.The LRO works by aggregating the incoming TCP and UDP packets into larger packets inside the NI's buffer. The receiving side software has been improved to support out-of-order packets. The second proposed software solution is applied on the Large Send Offload (LSO). The proposed LSO function processing is implemented by segmenting TCP and UDP messages that are larger than the Maximum Transmission Unit to the Maximum Segment Size. New packet headers are generatedfor each new outgoing packet. A scalable programmable NI based 32-bit RISC core is presented that can support 100 Gbps network speeds. Acceleration of the processing time frame required at the NI has been implemented to prevent hazards (such as Data Hazard and Control Hazard) during the execution of the LRO and the LSO functions. An R2000/3000 RISC has been used in order to test the LRO and LSO functions and to discover the instruction set that is most suitable. Following this the VHDL NI was implemented with three pipeline RISC cores, a simple DMA controller and Content Addressable Memory. An evaluation of the desired RISC clock rate that is required to process TCP and UDP streams at 100 Gbps was conducted. It was determined that aRISC core running at 752 MHz with a DMA clock of 3753 MHz was able to process packets 512 bytes or larger fast enough to support 100 Gbps network speeds.

Research paper thumbnail of A RISC-based ATM network interface: processing, architecture, scalability and performance

Research paper thumbnail of Large Sending Offload: Design and Implementation for High-Speed Communications Rate Up to 100 GBPS

International journal of new computer architectures and their applications, 2013

With the release of P802.3ba IEEE, send and receive data at 40 Gbps to 100 Gbps could become poss... more With the release of P802.3ba IEEE, send and receive data at 40 Gbps to 100 Gbps could become possible. Offloading part of the processing protocol to the network card showed success in sending data at high speeds up to 10 Gbps. Eventually, by enhancing transmission processing and taking advantage of the high speed, a potential network interface structure and performance needs to be addressed and implemented in order to send packets quickly corresponding with 40 Gbps and 100 Gbps. In this paper, such a network interface that supports high speeds after 10 Gbps has been designed. An alternative Large Sending Offload algorithm for sending TCP/IP and UDP/IP packets has also been implemented. A cost-effective RISC processor and a simple DMA for data transfer have also been implemented and simulated and tested for high speed. The behavior model shows that, a 450 MHz RISC core can support the sending-side processing up to 100 Gbps transmission speed for the TCP/IP and UDP/IP protocol when the MTU is 512 bytes or larger. A DMA with 2115 MHz is required to eliminate the idle cycles while transferring data over the 64-bit local bus.

Research paper thumbnail of Science Education in Libya

Science Education in Countries Along the Belt & Road, 2022

This chapter provides a brief introduction to the geographical location of Libya, its population ... more This chapter provides a brief introduction to the geographical location of Libya, its population and the current political system. We highlight the levels of the education system in Libya (primary, basic and higher education). This includes the number of enrolled students and the number of dropout rates per year. Training and development in some schools and universities that have established eLearning and emerging technologies to enhance science education teaching or learning are discussed. The assessment methodology is also considered. The chapter also provides some statistics about the economic situation technologies and cultural development in Libya. Challenges, strategies, reflections, issues, and future paths form the latter part of this chapter.

Research paper thumbnail of A RISC-based ATM network interface: processing, architecture, scalability and performance

Research paper thumbnail of Design a scalable ethernet Network Interface supporting the Large Receive Offload

2012 International Symposium on Communications and Information Technologies (ISCIT), 2012

The Ethernet speed has increased to 40-100 Gbps since the release of IEEE P802.3ba. In this paper... more The Ethernet speed has increased to 40-100 Gbps since the release of IEEE P802.3ba. In this paper, we have enhanced the Intel's Large Receive Offload Linux software driver function to manage the out-of-order packets and designed a scalable Network Interface based RISC core to support this function in the Network Interface. The RISC's performance and data movements for high communication rates up to 100 Gbps have been measured, and the results presented herein show that a cost-effective embedded RISC core can provide the required efficiency of the network interface to support a wide range of transmission line speeds, up to 100 Gbps. Furthermore, we have found several techniques that can contribute to packet processing and work with fewer headers and less data copying in a host memory.

Research paper thumbnail of An Evaluation of TCP and UDP Protocols Processing Required for Network Interface Design at 100 Gbps

2011 IEEE International Conference on High Performance Computing and Communications, 2011

Today major challenges are faced by server platforms while performing TCP/IP or UDP/IP protocol p... more Today major challenges are faced by server platforms while performing TCP/IP or UDP/IP protocol processing. For instance, the speed of networks now exceeds the gigabit per sec Gbps, the design and implementations of high-performance Network Interfaces (NI) have become very challenging. There are different possible design approaches to implement high-speed NI. However, using the General Purpose Processing (GPP) as a core engine to offload some, if not all, of the TCP/IP or UDP/IP protocol functions can deliver some important features to NIs, such as simplicity, scalability, shorter developing cycle time and reduced costs. Still it is not clear whether the GPP can provide the processing required for high-speed line over 10 Gbps. Also, where is the limit of such GPP in supporting the processing of network interfaces? In this paper, we have measured the amount of processing required for Ethernet Network Interfaces (ENI) design supporting different transmission line speeds. A NIprogrammable based RISC model has been designed to measure the processing required for the ENI|. The results have shown that a RISC core running at 240 MHz can be used as a processing core in high-speed ENI. Such core can support a wide range of transmission line speeds, up to 100 Gbps. Also, we have discussed some of the design issues that are related to RISC core based NI and the data movement type.

Research paper thumbnail of TCP and UDP processing requirements for network interface design at 100 Gbps

Today major challenges are faced by server platforms while processing TCP/IP or UDP/IP. For insta... more Today major challenges are faced by server platforms while processing TCP/IP or UDP/IP. For instance, the speed of networks now exceeds the gigabit per sec Gbps, the design and implementations of high-performance Network Interfaces (NI) have become very challenging. There are different possible design approaches to implement high-speed NI. However, using the General Purpose Processor (GPP) as a core engine to offload some, if not all, of the TCP/IP or UDP/IP protocol functions can deliver some important features to NIs, such as simplicity, scalability, shorter development cycle time and reduced costs. Still it is not clear whether the GPP can provide the processing required Ethernet beyond 10 Gbps. Also, what is the limit of such GPP in supporting the processing of network interfaces? In this paper, we have measured the amount of processing required for Ethernet Network Interfaces (ENI) supporting different transmission line speeds. A NI-programmable based RISC model has been designed to measure the processing required for the ENI. The results have shown that a RISC core running at 240 MHz can be used as a processing core in high-speed ENI. Such core can support a wide range of transmission line speeds, up to 100 Gbps. Also, we have discussed some of the design issues that are related to RISC core based NI and the data movement type.

Research paper thumbnail of Design and Simulating a Specialized Embedded Cores for UDP Network Interface Processing

Modelling and Simulation / 804: Signal and Image Processing, 2013

The speed of Ethernet networks has increased to 40-100 Gbps since the release of IEEE P802.3ba. E... more The speed of Ethernet networks has increased to 40-100 Gbps since the release of IEEE P802.3ba. Enhancing the protocol processing at the end node is essential to meet the demands of the increased network speeds. This research presents an enhanced pre-packet processing for inbound and outbound processing using a scalable Network Interface-based three-pipeline Embedded Processor. The designed Network Interfaces uses a specialized cost-effective 760 MHz embedded processor core can support a wide range of received UDP/IP packets, up to 100 Gbps. A 430 MHz Embedded Processor can be used for the send side. Furthermore, we have provided a processing methodology for Large Receive Offload and Large Send Offload that can contribute to pre-packet processing and work with fewer headers and data transfer from the network interface.