Nadine Collaert - Profile on Academia.edu (original) (raw)
Papers by Nadine Collaert
Gate-edge charges related effects and performance degradation in advanced multiple-gate MOSFETs
Solid-State Electronics, 2011
This paper analyzes the influence of negative charges (NC) located at the gate edges on the advan... more This paper analyzes the influence of negative charges (NC) located at the gate edges on the advanced MOSFETs behavior, paying particular attention to the subthreshold slope, S, maximum transconductance, Gmmax, and analog figures of merit, such as transconductance over drain current ratio, Gm/ID, output conductance, GD, Early voltage, VEA, and intrinsic gain. General trends obtained by two-dimensional numerical simulations on double-gate (DG) structures are whenever possible qualitatively correlated with experimental data ...
(Invited) Stress Simulations of Si- and Ge-Channel FinFETs for the 14 nm-Node and Beyond
ECS Transactions, 2013
This work studies the effectiveness of stressors for Si- and Ge-channel gate-last FinFETs in nest... more This work studies the effectiveness of stressors for Si- and Ge-channel gate-last FinFETs in nested layouts with dimensions of the 14, 10 and 7 nm-nodes. P-type FinFETs with Si-channels can be efficiently boosted by SiGe source/drain (S/D) stressors, and provide higher mobility than relaxed Ge-channel pFinFETs. The highest pFET mobility is found for strained Ge-channels: in this case a SiGe Strain-Relaxed Buffer (SRB) with Ge < 90% leads to a channel mobility that is significantly higher than what is achievable with strained Si. For nFETs, a SiGe-SRB is the most efficient booster for Si-channels. Theoretically, the electron mobility of Ge fin sidewalls is very high, making Ge-channel nFinFETs a promising alternative, even without strain. SRBs are the most efficient stressors and are scalable beyond the 14 nm-node. Etching the fins in the S/D regions releases strain generated by the SRB, therefore raised S/D stressors are preferred over recessed for maximal mobility when combined ...
Fabrication of 50 nm high performance strained-SiGe pMOSFETs with selective epitaxial growth
Applied surface …, 2004
Implementation of strained SiGe in pMOSFETs provides up to 85% higher hole mobilities and 55% and... more Implementation of strained SiGe in pMOSFETs provides up to 85% higher hole mobilities and 55% and 13% higher on-state currents for 10 μm and 70 nm channel lengths. Low leakage current, good Short Channel and Drain Induced Barrier Lowering behavior are obtained. ...
Fabrication and Analysis of a ${\rm Si}/{\rm Si}_{0.55}{\rm Ge}_{0.45}$ Heterojunction Line Tunnel FET
IEEE Transactions on Electron Devices, 2000
ABSTRACT This paper presents a new integration scheme to fabricate a Si/Si0.55Ge0.45 heterojuncti... more ABSTRACT This paper presents a new integration scheme to fabricate a Si/Si0.55Ge0.45 heterojunction line tunnel field effect transistor (TFET). The device shows an increase in tunneling current with gate length. The 1-μm gate length device shows ON current in excess of 20 μA/μm at VGS = VDS = 1.2 V. Low-temperature measurements, performed to suppress trap-assisted tunneling (TAT), reveal the point subthreshold swing as low as 22 mV/dec at 78 K. Field-induced quantum confinement effects are found to increase the tunneling onset voltage by ~0.35 V. Variation of the tunneling onset voltage measured experimentally is correlated to variation in the pocket thickness and its doping concentration. Small geometry devices were found to be more susceptible to microvariations in the pocket thickness and doping concentration.
Low frequency noise characterisation of submicron vertical heterojuncton pMOSFETs
Results of the low frequency noise characterisation of Si/Si'_xGex vertical heterojunction p... more Results of the low frequency noise characterisation of Si/Si'_xGex vertical heterojunction pMOSFETs with a channel length of 120 nm are presented. Devices with different Ge-concentration s were measured to investigate the influence of the barrier height on, the noise behaviour of the devices. The observed low frequency noise exhibits a l/f shape for the heterojunction devices and a strongly deviating behaviour for their Si-only counte rparts.
Modern MOSFET devices with undoped channel have a non-trivial current distribution, which is gate... more Modern MOSFET devices with undoped channel have a non-trivial current distribution, which is gate voltage dependent. In our work we have studied the sub-threshold behavior of undoped triple gate MOSFETs (FinFETs) using a thermionic transport model. We have analyzed the conductance data of such devices, and from this, we have been able to determine the evolution of both the active cross-section area of the channel and the barrier height as a function of the gate voltage. The result of our experiments shows good agreement with tight binding simulations and with analytical results. This confirms the validity of the use of our thermionic approach to study transport in sub-micrometer size FinFET devices and not only in micrometer size samples specially made for characterizations.
Journal of Integrated Circuits and Systems
The device architecture dilemma for CMOS technologies: Opportunities & challenges of finFET over planar MOSFET
2009 International Symposium on VLSI Technology, Systems, and Applications, 2009
... B. Parvais, A. Mercha, N. Collaert, R. Rooyackers, I. Ferain, M. Jurczak, V. Subramanian, A. ... more ... B. Parvais, A. Mercha, N. Collaert, R. Rooyackers, I. Ferain, M. Jurczak, V. Subramanian, A. De Keersgieter, T. Chiarella, C. Kerner, L. Witters, S. Biesemans and T. Hoffman IMEC, Kapeldreef 75, 3001 Leuven, Belgium Phone: +32 16 28 83 18, Fax: +32 16 ... In ve rte rd ela y [p s] ...
A novel low-voltage biasing scheme for double gate FBC achieving 5s retention and 1016 endurance at 85°C
2010 International Electron Devices Meeting, 2010
We demonstrate a novel low-voltage biasing scheme on ultra-thin BOX (UTBOX) FDSOI floating body c... more We demonstrate a novel low-voltage biasing scheme on ultra-thin BOX (UTBOX) FDSOI floating body cells with Lg=55nm and tSi=20nm. By optimizing the front and back gate biasing to enhance the positive feedback loop, the required VDS can be reduced to 1.5V while retention times as high as 5s can still be achieved at 85°C. For the first time, we also
Parasitic Source/Drain Resistance Reduction in N-channel SOI MuGFETs with 15nm Wide Fins
2005 IEEE International SOI Conference Proceedings, 2005
A. Dixit (1,2), K. G.Anil (1), N. Collaert (1), R. Rooyackers (1), F. Leys('), I. Ferain(t12... more A. Dixit (1,2), K. G.Anil (1), N. Collaert (1), R. Rooyackers (1), F. Leys('), I. Ferain(t12), A. De Keersgieter (1), TY Hoffnann (1), R. Loo(l), M. Goodwin (3), P. Zimmerman (4), M. Caymax (1), K. De Meyer (1,2), M. Jurczak (), and S. Biesemans (1) (1) IMEC, Kapeldreef 75, B-3001 Heverlee, ...
Engineering Materials, 2011
FinFET is a promising device structure for scaled CMOS logic/memory applications in 22 nm technol... more FinFET is a promising device structure for scaled CMOS logic/memory applications in 22 nm technology and beyond, thanks to its good short channel effect (SCE) controllability and its small variability. Scaled SRAM and analog circuit are promising candidates for finFET applications and some demonstrations for them are already reported. On the other hand, for finFETs production, quite a lot of process challenges are required due to difficult fin/gate patterning in the 3D structure, conformal doping to fin and high access resistance in extremely thin body, etc. The fin/gate patterning can be improved by optimization of patterning stack, patterning scheme and etch chemistry. Alternative doping techniques show good conformal doping in 3D structure in finFETs. High access resistance is reduced by junction optimization and strain boaster technique.
Successful Selective Epitaxial Si[sub 1−x]Ge[sub x] Deposition Process for HBT-BiCMOS and High Mobility Heterojunction pMOS Applications
ABSTRACT
Special issue Section-ULIS 2004 - Foreword
Solid-State Electronics
Understanding the optimization of sub-45nm FinFET devices for ESD applications
2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2007
ABSTRACT ESD performance of advanced FinFETs shows a delicate sensitivity to device layout and to... more ABSTRACT ESD performance of advanced FinFETs shows a delicate sensitivity to device layout and to processing. Thermal issues are experimentally correlated to gate length, fin width, electrical operation mode and are investigated by TCAD simulation. S/D implant conditions, silicide blocking, and selective epitaxial growth are studied. Reasonable ESD performance is demonstrated while margins between success and failure seem to be very narrow.
GIDL (gate-induced drain leakage) and parasitic schottky barrier leakage elimination in aggressively scaled HfO/sub 2/TiN FinFET devices
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., 2005
Abstract We demonstrate that for aggressively scaled FinFETs, with 2nm HfO 2 and TiN metal gate (... more Abstract We demonstrate that for aggressively scaled FinFETs, with 2nm HfO 2 and TiN metal gate (ie, workfunction close to midgap), several parasitic leakage mechanisms that impact the off-state current become dominant. We provide a detailed characterization of ...
Analysis of sense margin and reliability of 1T-DRAM fabricated on thin-film UTBOX substrates
2009 IEEE International SOI Conference, 2009
In this work, we have investigated the impact of back bias on the behavior of UTBOX IT-DRAM. The ... more In this work, we have investigated the impact of back bias on the behavior of UTBOX IT-DRAM. The back bias impacts the behavior of undoped and doped channels differently thereby leading to different optimization schemes. It was also shown that by careful optimization of the bias conditions for both "1" but also "0", the device degradation due to hot carrier
Technology/System Codesign and Benchmarking for Lateral and Vertical GAA Nanowire FETs at 5-nm Technology Node
IEEE Transactions on Electron Devices, 2015
ABSTRACT
High-temperature characterization of advanced strained nMuGFETs
(Invited) Selective-Area Metal Organic Vapor-Phase Epitaxy of InGaAs/InP Heterostrucures on Si for Advanced CMOS Devices
ECS Transactions, 2014
2010 Symposium on VLSI Technology, 2010
Atom probe tomography (APT) in conjunction with scanning spreading resistance microscopy (SSRM) i... more Atom probe tomography (APT) in conjunction with scanning spreading resistance microscopy (SSRM) is demonstrated for the first time to profile dopant and carrier distributions in FinFET-based devices with sub-nanometer resolution. These two techniques together provide information on the degree of conformality, the dose retention and the dopant activation. These results are also compared with a methodology involving secondary ion mass spectrometry (SIMS). Ion implantation for increased conformality of source/drain extensions is demonstrated for tilted implants, which clearly leads to improved device performance.
Gate-edge charges related effects and performance degradation in advanced multiple-gate MOSFETs
Solid-State Electronics, 2011
This paper analyzes the influence of negative charges (NC) located at the gate edges on the advan... more This paper analyzes the influence of negative charges (NC) located at the gate edges on the advanced MOSFETs behavior, paying particular attention to the subthreshold slope, S, maximum transconductance, Gmmax, and analog figures of merit, such as transconductance over drain current ratio, Gm/ID, output conductance, GD, Early voltage, VEA, and intrinsic gain. General trends obtained by two-dimensional numerical simulations on double-gate (DG) structures are whenever possible qualitatively correlated with experimental data ...
(Invited) Stress Simulations of Si- and Ge-Channel FinFETs for the 14 nm-Node and Beyond
ECS Transactions, 2013
This work studies the effectiveness of stressors for Si- and Ge-channel gate-last FinFETs in nest... more This work studies the effectiveness of stressors for Si- and Ge-channel gate-last FinFETs in nested layouts with dimensions of the 14, 10 and 7 nm-nodes. P-type FinFETs with Si-channels can be efficiently boosted by SiGe source/drain (S/D) stressors, and provide higher mobility than relaxed Ge-channel pFinFETs. The highest pFET mobility is found for strained Ge-channels: in this case a SiGe Strain-Relaxed Buffer (SRB) with Ge < 90% leads to a channel mobility that is significantly higher than what is achievable with strained Si. For nFETs, a SiGe-SRB is the most efficient booster for Si-channels. Theoretically, the electron mobility of Ge fin sidewalls is very high, making Ge-channel nFinFETs a promising alternative, even without strain. SRBs are the most efficient stressors and are scalable beyond the 14 nm-node. Etching the fins in the S/D regions releases strain generated by the SRB, therefore raised S/D stressors are preferred over recessed for maximal mobility when combined ...
Fabrication of 50 nm high performance strained-SiGe pMOSFETs with selective epitaxial growth
Applied surface …, 2004
Implementation of strained SiGe in pMOSFETs provides up to 85% higher hole mobilities and 55% and... more Implementation of strained SiGe in pMOSFETs provides up to 85% higher hole mobilities and 55% and 13% higher on-state currents for 10 μm and 70 nm channel lengths. Low leakage current, good Short Channel and Drain Induced Barrier Lowering behavior are obtained. ...
Fabrication and Analysis of a ${\rm Si}/{\rm Si}_{0.55}{\rm Ge}_{0.45}$ Heterojunction Line Tunnel FET
IEEE Transactions on Electron Devices, 2000
ABSTRACT This paper presents a new integration scheme to fabricate a Si/Si0.55Ge0.45 heterojuncti... more ABSTRACT This paper presents a new integration scheme to fabricate a Si/Si0.55Ge0.45 heterojunction line tunnel field effect transistor (TFET). The device shows an increase in tunneling current with gate length. The 1-μm gate length device shows ON current in excess of 20 μA/μm at VGS = VDS = 1.2 V. Low-temperature measurements, performed to suppress trap-assisted tunneling (TAT), reveal the point subthreshold swing as low as 22 mV/dec at 78 K. Field-induced quantum confinement effects are found to increase the tunneling onset voltage by ~0.35 V. Variation of the tunneling onset voltage measured experimentally is correlated to variation in the pocket thickness and its doping concentration. Small geometry devices were found to be more susceptible to microvariations in the pocket thickness and doping concentration.
Low frequency noise characterisation of submicron vertical heterojuncton pMOSFETs
Results of the low frequency noise characterisation of Si/Si'_xGex vertical heterojunction p... more Results of the low frequency noise characterisation of Si/Si'_xGex vertical heterojunction pMOSFETs with a channel length of 120 nm are presented. Devices with different Ge-concentration s were measured to investigate the influence of the barrier height on, the noise behaviour of the devices. The observed low frequency noise exhibits a l/f shape for the heterojunction devices and a strongly deviating behaviour for their Si-only counte rparts.
Modern MOSFET devices with undoped channel have a non-trivial current distribution, which is gate... more Modern MOSFET devices with undoped channel have a non-trivial current distribution, which is gate voltage dependent. In our work we have studied the sub-threshold behavior of undoped triple gate MOSFETs (FinFETs) using a thermionic transport model. We have analyzed the conductance data of such devices, and from this, we have been able to determine the evolution of both the active cross-section area of the channel and the barrier height as a function of the gate voltage. The result of our experiments shows good agreement with tight binding simulations and with analytical results. This confirms the validity of the use of our thermionic approach to study transport in sub-micrometer size FinFET devices and not only in micrometer size samples specially made for characterizations.
Journal of Integrated Circuits and Systems
The device architecture dilemma for CMOS technologies: Opportunities & challenges of finFET over planar MOSFET
2009 International Symposium on VLSI Technology, Systems, and Applications, 2009
... B. Parvais, A. Mercha, N. Collaert, R. Rooyackers, I. Ferain, M. Jurczak, V. Subramanian, A. ... more ... B. Parvais, A. Mercha, N. Collaert, R. Rooyackers, I. Ferain, M. Jurczak, V. Subramanian, A. De Keersgieter, T. Chiarella, C. Kerner, L. Witters, S. Biesemans and T. Hoffman IMEC, Kapeldreef 75, 3001 Leuven, Belgium Phone: +32 16 28 83 18, Fax: +32 16 ... In ve rte rd ela y [p s] ...
A novel low-voltage biasing scheme for double gate FBC achieving 5s retention and 1016 endurance at 85°C
2010 International Electron Devices Meeting, 2010
We demonstrate a novel low-voltage biasing scheme on ultra-thin BOX (UTBOX) FDSOI floating body c... more We demonstrate a novel low-voltage biasing scheme on ultra-thin BOX (UTBOX) FDSOI floating body cells with Lg=55nm and tSi=20nm. By optimizing the front and back gate biasing to enhance the positive feedback loop, the required VDS can be reduced to 1.5V while retention times as high as 5s can still be achieved at 85°C. For the first time, we also
Parasitic Source/Drain Resistance Reduction in N-channel SOI MuGFETs with 15nm Wide Fins
2005 IEEE International SOI Conference Proceedings, 2005
A. Dixit (1,2), K. G.Anil (1), N. Collaert (1), R. Rooyackers (1), F. Leys('), I. Ferain(t12... more A. Dixit (1,2), K. G.Anil (1), N. Collaert (1), R. Rooyackers (1), F. Leys('), I. Ferain(t12), A. De Keersgieter (1), TY Hoffnann (1), R. Loo(l), M. Goodwin (3), P. Zimmerman (4), M. Caymax (1), K. De Meyer (1,2), M. Jurczak (), and S. Biesemans (1) (1) IMEC, Kapeldreef 75, B-3001 Heverlee, ...
Engineering Materials, 2011
FinFET is a promising device structure for scaled CMOS logic/memory applications in 22 nm technol... more FinFET is a promising device structure for scaled CMOS logic/memory applications in 22 nm technology and beyond, thanks to its good short channel effect (SCE) controllability and its small variability. Scaled SRAM and analog circuit are promising candidates for finFET applications and some demonstrations for them are already reported. On the other hand, for finFETs production, quite a lot of process challenges are required due to difficult fin/gate patterning in the 3D structure, conformal doping to fin and high access resistance in extremely thin body, etc. The fin/gate patterning can be improved by optimization of patterning stack, patterning scheme and etch chemistry. Alternative doping techniques show good conformal doping in 3D structure in finFETs. High access resistance is reduced by junction optimization and strain boaster technique.
Successful Selective Epitaxial Si[sub 1−x]Ge[sub x] Deposition Process for HBT-BiCMOS and High Mobility Heterojunction pMOS Applications
ABSTRACT
Special issue Section-ULIS 2004 - Foreword
Solid-State Electronics
Understanding the optimization of sub-45nm FinFET devices for ESD applications
2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2007
ABSTRACT ESD performance of advanced FinFETs shows a delicate sensitivity to device layout and to... more ABSTRACT ESD performance of advanced FinFETs shows a delicate sensitivity to device layout and to processing. Thermal issues are experimentally correlated to gate length, fin width, electrical operation mode and are investigated by TCAD simulation. S/D implant conditions, silicide blocking, and selective epitaxial growth are studied. Reasonable ESD performance is demonstrated while margins between success and failure seem to be very narrow.
GIDL (gate-induced drain leakage) and parasitic schottky barrier leakage elimination in aggressively scaled HfO/sub 2/TiN FinFET devices
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., 2005
Abstract We demonstrate that for aggressively scaled FinFETs, with 2nm HfO 2 and TiN metal gate (... more Abstract We demonstrate that for aggressively scaled FinFETs, with 2nm HfO 2 and TiN metal gate (ie, workfunction close to midgap), several parasitic leakage mechanisms that impact the off-state current become dominant. We provide a detailed characterization of ...
Analysis of sense margin and reliability of 1T-DRAM fabricated on thin-film UTBOX substrates
2009 IEEE International SOI Conference, 2009
In this work, we have investigated the impact of back bias on the behavior of UTBOX IT-DRAM. The ... more In this work, we have investigated the impact of back bias on the behavior of UTBOX IT-DRAM. The back bias impacts the behavior of undoped and doped channels differently thereby leading to different optimization schemes. It was also shown that by careful optimization of the bias conditions for both "1" but also "0", the device degradation due to hot carrier
Technology/System Codesign and Benchmarking for Lateral and Vertical GAA Nanowire FETs at 5-nm Technology Node
IEEE Transactions on Electron Devices, 2015
ABSTRACT
High-temperature characterization of advanced strained nMuGFETs
(Invited) Selective-Area Metal Organic Vapor-Phase Epitaxy of InGaAs/InP Heterostrucures on Si for Advanced CMOS Devices
ECS Transactions, 2014
2010 Symposium on VLSI Technology, 2010
Atom probe tomography (APT) in conjunction with scanning spreading resistance microscopy (SSRM) i... more Atom probe tomography (APT) in conjunction with scanning spreading resistance microscopy (SSRM) is demonstrated for the first time to profile dopant and carrier distributions in FinFET-based devices with sub-nanometer resolution. These two techniques together provide information on the degree of conformality, the dose retention and the dopant activation. These results are also compared with a methodology involving secondary ion mass spectrometry (SIMS). Ion implantation for increased conformality of source/drain extensions is demonstrated for tilted implants, which clearly leads to improved device performance.