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Papers by Nasserdine Zergainoh

2017 18th IEEE Latin American Test Symposium (LATS)

IEEE Transactions on Nuclear Science

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

VLSI Design

3D integration can greatly benefit future many-cores by enabling low-latency three-dimensional Ne... more 3D integration can greatly benefit future many-cores by enabling low-latency three-dimensional Network-on-Chip (3D-NoC) topologies. However, due to high cost, low yield, and frequent failures of Through-Silicon Via (TSV), 3D-NoCs are most likely to include only a few vertical connections, resulting in incomplete topologies that pose new challenges in terms of deadlock-free routing and TSV assignment. The routers of such networks require a way to locate the nodes that have vertical connections, commonly known as elevators, and select one of them in order to be able to reach other layers when necessary. In this paper, several alternative TSV selection strategies requiring a constant amount of configurable bits per router are introduced. Each proposed solution consists of a configuration algorithm, which provides each router with the necessary information to locate the elevators, and a routing algorithm, which uses this information at runtime to route packets to an elevator. Our algori...

IEEE Transactions on Emerging Topics in Computing

IEEE Transactions on Computers

IEEE Transactions on Nanotechnology

IEEE Transactions on Nuclear Science

IEEE Transactions on Nuclear Science, 2017

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2016

2016 21th IEEE European Test Symposium (ETS), 2016

IEEE Transactions on Nuclear Science, 2016

The aim of this work is to evaluate the SEE sensitivity of a multi-core processor having implemen... more The aim of this work is to evaluate the SEE sensitivity of a multi-core processor having implemented ECC and parity in their cache memories. Two different application scenarios are studied. The first one configures the multi-core in Asymmetric Multi-Processing mode running a memory-bound application, whereas the second one uses the Symmetric Multi-Processsing mode running a CPU-bound application. The experiments were validated through radiation ground testing performed with 14 MeV neutrons on the Freescale P2041 multi-core manufactured in 45nm SOI technology. A deep analysis of the observed errors in cache memories was carried-out in order to reveal vulnerabilities in the cache protection mechanisms. Critical zones like tag addresses were affected during the experiments. In addition, the results show that the sensitivity strongly depends on the application and the multi-processsing mode used.

2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012

This session brings together specialists from the DfT, DfY and DfR domains that will address key ... more This session brings together specialists from the DfT, DfY and DfR domains that will address key problems together with their solutions for the 14nm node and beyond, dealing with extremely complex chips affected by high defect levels, unpredictable and heterogeneous timing behavior, circuit degradation over time, including extreme situations related with the ultimate CMOS nodes, where all processor nodes, routers and links of single-chip massively parallel tera-device processors could comprise timing faults (such as delay faults or clock skews); a large percentage of these parts are affected by catastrophic failures; all parts experience significant performance degradations over time; and new catastrophic failures occur at low MTBF.

Proceedings 11th International Workshop on Rapid System Prototyping. RSP 2000. Shortening the Path from Specification to Prototype (Cat. No.PR00668), 2000

In this paper, we present a new methodology to rapidly explore the large design space encountered... more In this paper, we present a new methodology to rapidly explore the large design space encountered in hardware/software systems. The proposed methodology is based on a fast and accurate estimation approach. It has been implemented as an extension to a hardware/software codesign flow to enable the exploration of a large number of multiprocessor architecture solutions from the very start of the design process. The effectiveness of this approach is illustrated by a significant application example.

1998 URSI International Symposium on Signals, Systems, and Electronics. Conference Proceedings (Cat. No.98EX167), 2000

This paper discusses the uses of SDL for the co-design of an ATM Network Interface Card (NIC). In... more This paper discusses the uses of SDL for the co-design of an ATM Network Interface Card (NIC). In this study, the initial specification is given in SDL. The architecture generation is made using Cosmos, a co-design tool for multiprocessor architecture. Several architectures are produced starting from the same initial SDL specification. The performance evaluation of these solutions was made using hardware/software cosimulation. This paper describes the experiment and the lessons learned about the capabilities and the restrictions of SDL and Cosmos for hardware/software co-design of distributed systems. The use of SDL allows for drastic reduction of the model size when compared to hardware/software model given in C/VHDL. SDL simulation may be 30 times faster than C/VHDL simulation.

Proceedings Tenth IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype (Cat. No.PR00246), 2000

... Page 4. This model enables the user to describe a wide range of communications protocols and ... more ... Page 4. This model enables the user to describe a wide range of communications protocols and most system level communication, such as message passing or shared memory. 4 Communication Refinement ... [20] AA Jerraya, M. Romdhani, CA Valderrama, Ph. ...

Proceedings of the 10th Great Lakes Symposium on VLSI - GLSVLSI '00, 2000

This paper illustrates an approach to design and validation of heterogeneous systems. The emphasi... more This paper illustrates an approach to design and validation of heterogeneous systems. The emphasis is placed on devices which incorporate MEMS parts in either a single mixed-technology (CMOS + micromachining) SOC device, or alternatively as a hybrid system with the MEMS part in a separate chip. The design flow is general, and it is illustrated for the case of applications embedding CMOS sensors. In particular, applications based on fingerprint recognition are considered since a rich variety of sensors and data processing algorithms can be considered. A high level multilanguage/multi-engine approach is used for system specification and co-simulation. This also allows for an initial high-level architecture exploration, according to performance and cost requirements imposed by the target application. Thermal simulation of the overall device, including packaging, is also considered since this can have a significant impact in sensor performance. From the selected system specification, the actual architecture is finally generated via a multi-language co-design approach which can result in both hardware and software parts. The hardware parts are composed of available IP cores. For the case of a single chip implementation, the most important issue of embedded-core-based testing is briefly considered, and current techniques are adapted for testing the embedded cores in the SOC devices discussed.

2015 15th European Conference on Radiation and Its Effects on Components and Systems (RADECS), 2015

Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, 2001

In this paper, we present a novel approach for the design of application specific multiprocessor ... more In this paper, we present a novel approach for the design of application specific multiprocessor systems-onchip. Our approach is based on a generic architecture model which is used as a template throughout the design process. The key characteristics of this model are its great modularity, flexibility and scalability which make it reusable for a large class of applications. In addition, it allows to accelerate the design cycle. This paper focuses on the definition of the architecture model and the systematic design flow that can be automated. The feasibility and effectiveness of this approach are illustrated by two significant demonstration examples.

Architecture and Design of Distributed Embedded Systems, 2001