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Papers by Natarajan Shankar

Research paper thumbnail of The Correctness of a Code Generator for a Functional Language

Code generation is gaining popularity as a technique to bridge the gap between high-level models ... more Code generation is gaining popularity as a technique to bridge the gap between high-level models and executable code. We describe the theory underlying the PVS2C code generator that translates functional programs written using the PVS specification language to standalone, efficiently executable C code. We outline a correctness argument for the code generator. The techniques used are quite generic and can be applied to transform programs written in functional languages into imperative code. We use a formal model of reference counting to capture memory management and safe destructive updates for a simple first-order functional language with arrays. We exhibit a bisimulation between the functional execution and the imperative execution. This bisimulation shows that the generated imperative program returns the same result as the functional program.

Research paper thumbnail of PVS prover guide

Research paper thumbnail of PVS system guide

Research paper thumbnail of The PVS Specification Language

, 16completion analysis, 33CONJECTURE, 16conservative extension, 13constants, 12--13CONTAINING, 1... more , 16completion analysis, 33CONJECTURE, 16conservative extension, 13constants, 12--13CONTAINING, 18COROLLARY, 16curried applications, 25declarations, 9--16formulas, 16multiple, 9dependent types, 21--26empty types, 18enumeration types, 10, 12equality, 22EXISTS, 25exporting, 9expression, 29expressions, 22f91, 14FACT, 16FALSE, 22FORALL, 25formal parameters, see theory parametersFORMULA, 16formula declarations, 16function types, 19--20...

Research paper thumbnail of Metamathematics, machines, and Gödel's proof

Computers & Mathematics with Applications, 1997

Research paper thumbnail of Invited paper for FLoC'02. Appears in the Proceedings of FME'02, LNCS

Research paper thumbnail of Automated deduction for verification

ACM Computing Surveys, 2009

... successors (WS2S) [Ohlbach et al. 2001]. Modal and temporal logics are surveyed by Goldblatt ... more ... successors (WS2S) [Ohlbach et al. 2001]. Modal and temporal logics are surveyed by Goldblatt [1992], Mints [1992], Emerson [1990], and Blackburn et al. [2002]. Applications. Propositional logic has innumerable applications ...

Research paper thumbnail of A Mechanized Refinement Proof for a Garbage Collector

Research paper thumbnail of Effective Theorem Proving for Hardware Verification

Research paper thumbnail of Embedded deduction with ICS

Research paper thumbnail of PDPAR 2004 Preliminary Version

Most verification approaches assume a mathematical formalism in which functionsare total, even th... more Most verification approaches assume a mathematical formalism in which functionsare total, even though partial functions occur naturally in many applications. Furthermore, although there have been various proposals for logics of partial functions, there is no consensus on which is" the right" logic to use for verification applications. In this paper, we propose using a three-valued Kleene logic, where partialfunctions return the" undefined" value when applied outside of their domains. Theparticular semantics are chosen according to the principle of ...

Research paper thumbnail of To be presented at the National Security Agency's third High Confidence Software and Systems

Research paper thumbnail of Slicing SAL

Research paper thumbnail of Industrial Strength Formal Verification Techniques for Hardware Designs

The past decade has seen tremendous progress in the application of formal methods for hardware de... more The past decade has seen tremendous progress in the application of formal methods for hardware design and verification. While a number of different techniques based on BDDs, symbolic simulation, special-purpose decision procedures, model checking, and theorem proving have been applied with varying degrees of success, no one technique by itself has proven to be effective enough to verify a complex

Research paper thumbnail of An Integration of Model Checking with Automated Proof Checking

Research paper thumbnail of A tutorial introduction to PVS

Research paper thumbnail of A Tutorial on Using PVS for Hardware Verification

Research paper thumbnail of A tutorial on using PVS

Research paper thumbnail of An Integration of Model Checking and Proof Checking

Research paper thumbnail of Automatically Extracting Requirements Specifications from Natural Language

Natural language (supplemented with diagrams and some mathematical notations) is convenient for s... more Natural language (supplemented with diagrams and some mathematical notations) is convenient for succinct communication of technical descriptions between the various stakeholders (e.g., customers, designers, implementers) involved in the design of software systems. However, natural language descriptions can be informal, incomplete, imprecise and ambiguous, and cannot be processed easily by design and analysis tools. Formal languages, on the other hand, formulate design requirements in a precise and unambiguous mathematical notation, but are more difficult to master and use. We propose a methodology for connecting semi-formal requirements with formal descriptions through an intermediate representation. We have implemented this methodology in a research prototype called ARSENAL with the goal of constructing a robust, scalable, and trainable framework for bridging the gap between natural language requirements and formal tools. The main novelty of ARSENAL lies in its automated generation...

Research paper thumbnail of The Correctness of a Code Generator for a Functional Language

Code generation is gaining popularity as a technique to bridge the gap between high-level models ... more Code generation is gaining popularity as a technique to bridge the gap between high-level models and executable code. We describe the theory underlying the PVS2C code generator that translates functional programs written using the PVS specification language to standalone, efficiently executable C code. We outline a correctness argument for the code generator. The techniques used are quite generic and can be applied to transform programs written in functional languages into imperative code. We use a formal model of reference counting to capture memory management and safe destructive updates for a simple first-order functional language with arrays. We exhibit a bisimulation between the functional execution and the imperative execution. This bisimulation shows that the generated imperative program returns the same result as the functional program.

Research paper thumbnail of PVS prover guide

Research paper thumbnail of PVS system guide

Research paper thumbnail of The PVS Specification Language

, 16completion analysis, 33CONJECTURE, 16conservative extension, 13constants, 12--13CONTAINING, 1... more , 16completion analysis, 33CONJECTURE, 16conservative extension, 13constants, 12--13CONTAINING, 18COROLLARY, 16curried applications, 25declarations, 9--16formulas, 16multiple, 9dependent types, 21--26empty types, 18enumeration types, 10, 12equality, 22EXISTS, 25exporting, 9expression, 29expressions, 22f91, 14FACT, 16FALSE, 22FORALL, 25formal parameters, see theory parametersFORMULA, 16formula declarations, 16function types, 19--20...

Research paper thumbnail of Metamathematics, machines, and Gödel's proof

Computers & Mathematics with Applications, 1997

Research paper thumbnail of Invited paper for FLoC'02. Appears in the Proceedings of FME'02, LNCS

Research paper thumbnail of Automated deduction for verification

ACM Computing Surveys, 2009

... successors (WS2S) [Ohlbach et al. 2001]. Modal and temporal logics are surveyed by Goldblatt ... more ... successors (WS2S) [Ohlbach et al. 2001]. Modal and temporal logics are surveyed by Goldblatt [1992], Mints [1992], Emerson [1990], and Blackburn et al. [2002]. Applications. Propositional logic has innumerable applications ...

Research paper thumbnail of A Mechanized Refinement Proof for a Garbage Collector

Research paper thumbnail of Effective Theorem Proving for Hardware Verification

Research paper thumbnail of Embedded deduction with ICS

Research paper thumbnail of PDPAR 2004 Preliminary Version

Most verification approaches assume a mathematical formalism in which functionsare total, even th... more Most verification approaches assume a mathematical formalism in which functionsare total, even though partial functions occur naturally in many applications. Furthermore, although there have been various proposals for logics of partial functions, there is no consensus on which is" the right" logic to use for verification applications. In this paper, we propose using a three-valued Kleene logic, where partialfunctions return the" undefined" value when applied outside of their domains. Theparticular semantics are chosen according to the principle of ...

Research paper thumbnail of To be presented at the National Security Agency's third High Confidence Software and Systems

Research paper thumbnail of Slicing SAL

Research paper thumbnail of Industrial Strength Formal Verification Techniques for Hardware Designs

The past decade has seen tremendous progress in the application of formal methods for hardware de... more The past decade has seen tremendous progress in the application of formal methods for hardware design and verification. While a number of different techniques based on BDDs, symbolic simulation, special-purpose decision procedures, model checking, and theorem proving have been applied with varying degrees of success, no one technique by itself has proven to be effective enough to verify a complex

Research paper thumbnail of An Integration of Model Checking with Automated Proof Checking

Research paper thumbnail of A tutorial introduction to PVS

Research paper thumbnail of A Tutorial on Using PVS for Hardware Verification

Research paper thumbnail of A tutorial on using PVS

Research paper thumbnail of An Integration of Model Checking and Proof Checking

Research paper thumbnail of Automatically Extracting Requirements Specifications from Natural Language

Natural language (supplemented with diagrams and some mathematical notations) is convenient for s... more Natural language (supplemented with diagrams and some mathematical notations) is convenient for succinct communication of technical descriptions between the various stakeholders (e.g., customers, designers, implementers) involved in the design of software systems. However, natural language descriptions can be informal, incomplete, imprecise and ambiguous, and cannot be processed easily by design and analysis tools. Formal languages, on the other hand, formulate design requirements in a precise and unambiguous mathematical notation, but are more difficult to master and use. We propose a methodology for connecting semi-formal requirements with formal descriptions through an intermediate representation. We have implemented this methodology in a research prototype called ARSENAL with the goal of constructing a robust, scalable, and trainable framework for bridging the gap between natural language requirements and formal tools. The main novelty of ARSENAL lies in its automated generation...