Nilesh Mohota - Academia.edu (original) (raw)

Papers by Nilesh Mohota

Journal of emerging technologies and innovative research, Jun 1, 2016

This paper presents a VLSI implementation of the Advanced Encryption Standard (AES) algorithm. Th... more This paper presents a VLSI implementation of the Advanced Encryption Standard (AES) algorithm. The AES is a Federal Information Processing Standard (FIPS), which is a cryptographic algorithm that is used to protect digital data. AES encryption and decryption requires a 128 bit wide input block and a 128 bit wide input key. Under the influence of a key schedule the input block is encrypted by transforming it in a unique way into a new block of same size. The major emphasis is on presenting a power and moreover an area optimized AES. For implementing AES Rijndael algorithm on FPGA we will choose VHDL as the design entry technique. Xilinx ISE Design Suite version 14.7 will be used for the Synthesis and Simulation of the code.

International Journal of Computer Network and Information Security, 2013

Fault attacks are powerful and efficient cryptanalysis techniques to find the secret key of the A... more Fault attacks are powerful and efficient cryptanalysis techniques to find the secret key of the Advanced Encryption Standard (AES) algorithm. These attacks are based on injecting faults into the structure of the AES to obtain the confidential information. To protect the AES implementation against these attacks, a number of countermeasures have been proposed. In this paper, we propose a fault detection scheme for the Advanced Encryption Standard. We present its details implementation in each transformation of the AES. The simulation results show that the fault coverage achieves 99.999% for the proposed scheme. Moreover, the proposed fault detection scheme has been implemented on Xilinx Virtex-5 FPGA. Its area overhead and frequency degradation have been compared and it is shown that the proposed scheme achieves a good performance in terms of area and frequency.

2019 9th International Conference on Emerging Trends in Engineering and Technology - Signal and Information Processing (ICETET-SIP-19)

LDPC codes are an important aspect of 5G communication systems. This paper presents high performa... more LDPC codes are an important aspect of 5G communication systems. This paper presents high performance design of Low-density parity-check decoder on reconfigurable FPGA. LDPC codes are one of the most efficient error correcting codes for implementation on FPGA. The main aim is to implement a low complexity architecture of the LDPC decoder on the FPGA (Field Programmable Gate Array). The two main components of LDPC are VNU and CNU. Our efficient decoding structure will reduce the complexity with the help of check node unit (CNU) and the variable node unit (VNU) using min-sum algorithm for getting fewer slice resources. Here, we have used multiplexed storage structure for storing nod message to get the result in minimum FPGA resources. LDPC is quite an integral part in deep space communications and its potential utilization in the area which is highly explored. In space data systems it is quite important to have a LDPC decoder which has both low complexity and high performance architecture. Therefore the low-complexity method becomes an efficient method to achieve the requirements put in future by many wired and wireless communication system.

2020 Fourth International Conference on Inventive Systems and Control (ICISC)

The aim of this proposed project is to make the democratic process simple for the students at the... more The aim of this proposed project is to make the democratic process simple for the students at the college level. Presently in our college, vote casting is performed by utilizing paper and counting is done manually so it expends students as well as educators valuable time, also there can be a possibility of error while tallying the cast votes. All this makes the vote casting process very dreary so in our project, the vote capturing and tallying is done on the web. It saves processing time, avoids human errors and there won’t be any invalid votes It has a basic user interface of application which attracts users. As this application is planned for students so verification happens on the basis of unique ID code which is the students’ registered ID, with this goal the students can cast their votes remotely from anyplace. This is a combo box application so it additionally comprises university question papers, syllabus, and college fundamental data or different activities of the college.

Orthogonal frequency division multiplexing (OFDM) is a popular method for high data rate wireless... more Orthogonal frequency division multiplexing (OFDM) is a popular method for high data rate wireless transmission. MIMO OFDM has many promising features which allow wireless devices to communicate at a higher data rate with reduced errors and hardware complexity. This paper describes a design and implementation of a baseband Orthogonal Frequency Division Multiplexing (OFDM) transceiver utilizing Multiple Input Multiple Output (MIMO) signal processing for increased data rate. Orthogonal frequency division multiplexing (OFDM) has become a popular technique for transmission of signals over wireless channels. OFDM may be viewed as using many slowly-modulated narrowband signals rather than one rapidly-modulated wideband signal. This work describes how implement an OFDM modem on FPGA using VHDL for a 31 subcarrier (channels) OFDM system using 64 points radix-4 FFT time decimation, a CORDIC implementation to perform the butterfly calculus, and each channel modulation will use a 4-QAM constell...

Journal of emerging technologies and innovative research, 2015

Road accidents on highways & in cities have made the technologists to deeply think & design an em... more Road accidents on highways & in cities have made the technologists to deeply think & design an embedded system which when installed on a vehicle will help to identify an accident & provide the emergency medical service to the victim at the earliest. Today thousands of people die due to road accidents. In this paper an attempt has been made to design such system using ARM7LPC2148, GPS receiver, GSM module and accelerometer sensor. The most important parameter is to reduce the time required by medical personal to reach the accident location. When an accident occurs, an SMS is sent to the nearest hospital, police station & to the owner of the vehicle. It contains the latitude & longitude of the accident location. With the help of GPS coordinates the medical personal will be able to reach the accident location at the earliest & we can save lives. One more important feature of this system is vehicle tracking. This project uses regulated 5V, 750Ma power supply. 7805 three terminal voltage...

Journal of emerging technologies and innovative research, 2018

We overview late improvements in the design of extensive limit content-addressable memory (CAM). ... more We overview late improvements in the design of extensive limit content-addressable memory (CAM). A CAM is a memory that executes the query table capacity in a solitary clock cycle utilizing committed examination circuitry. CAMs are particularly mainstream in organize switches for parcel sending and bundle characterization, however they are additionally helpful in an assortment of different applications that require rapid table query. The primary CAM-design challenge is to diminish power utilization related with the expansive measure of parallel dynamic circuitry, without yielding velocity or memory thickness. In this paper, we review CAMdesign strategies at the circuit level and at the structural level. At the circuit level, we review low-power coordinate line sensing systems and hunt line driving methodologies. At the engineering level we review three strategies for decreasing power utilization. Keyword: Content Addressable Memory(CAM), Matchline Pipelining, Matchline Sensing, NAND...

The current trend in technology has lead to the emergence of complex Systems-on-Chip (SoC). Tradi... more The current trend in technology has lead to the emergence of complex Systems-on-Chip (SoC). Traditionally, shared busses were used for communication between the different components in an SoC in which a communication link is shared between components in a time-division fashion, resulting in a communication latency. To overcome the limitations of common bus based design we have proposed Network-On-Chip based SoC architecture. The aim of this work is to present a modified architecture of the routing node to achieve higher area and power efficiency using changes at the RTL architecture level. FPGA implementation of 4x4 Router has been performed on Xilinx Spartan-3 FPGA XC3S400. ASIC implementation has been done using Design Compiler and IC compiler of SYNOPSYS with 90 nm SAED technology library. It was found that the proposed router has latency of 4 clock cycles, occupies 0.2 sq. mm of silicon area and operates at 500 Mhz frequency.

Journal of emerging technologies and innovative research, 2016

Journal of emerging technologies and innovative research, 2015

The automotive electronics systems technology has been changing very rapidly over the past few ye... more The automotive electronics systems technology has been changing very rapidly over the past few years. So the main aim of this paper to develop a advanced embedded based prototype for vehicle safety to diagnosis the parameters of the vehicle installed to any vehicle which is used to record parameters according to sensor used to analyze the accidental vehicle for future safety .this will help to construct safer vehicle driving, improving the treatment for crash victims, helping to driving schools to provide data for better and safer driving to avoid accidents, it also helps the insurance companies for the investigation of crash. So the death rate due to accident can be minimizing. So this explores the developing the in vehicle technology to monitor and analyze the real life driving behavior. Recorded data can also be used for forensics, revealing the problems that caused the accident and give manufacturer an idea for improvement. So the aim is to develop an embedded integrated system ...

International Journal on Recent and Innovation Trends in Computing and Communication, 2015

One of the foremost vital problems in communication customary is that the secure transport protoc... more One of the foremost vital problems in communication customary is that the secure transport protocols. This paper can offer a doable resolution for Rijindael's encryption and decoding algorithmic program using NIOS II processor, provided by ALTERA to be enforced in FPGA. We are going to see the performance of Rijindael's AES using NIOS II/e (economic), NIOS II/s (standard) and NIOS II/f (fast). The suggested system is capable of encrypting and decrypting 128,198 and 256 bits of data. The FPGA has the potential of data processing and hardware modification. The NIOS II is a versatile embedded processor family that represents high performance, lower overall cost, power consumption, complexity combining several functions into one chip. The look of the Rijindael algorithmic program supported "NIOS II + FPGA" are able to do a better processing speed whereas it occupies comparatively low resources. The inputs and the control of an AES algorithmic program is written in C language and is interfaced with the system using general purpose input and output (GPIO) and also the management part is enforced in software in NIOS II integrated development environment (IDE). The implementation is completed on Cyclone II FPGA kit. The results are analysed on the personnel computer (PC) in IDE console window.

IOSR Journal of Electronics and Communication Engineering, 2017

The importance of cryptography applied to security in electronic data transactions has acquired a... more The importance of cryptography applied to security in electronic data transactions has acquired an essential relevance during the last few years. A proposed FPGA-based implementation of the Advanced Encryption Standard(AES) algorithm along with key encryption for images is presented in this paper. An efficient image encryption scheme based on FPGA using AES algorithm integrated with RC4 encryption standard is proposed. The use of RC4 algorithm imparts additional level of security to the encryption. The design converts the original image into its hex values using Matlab and then give it as input to the proposed AES. The key input given to AES is further encrypted using RC4 encryption algorithm. The encrypted image is decrypted using AES decryption algorithm. The encrypted key is decrypted using RC4 decryption algorithm so as to give it as input to the AES decryption algorithm. The encrypted and decrypted image can be analysed in Matlab. The design uses an iterative looping approach with block and key size of 128 bits, lookup table implementation of S-box. This gives low complexity architecture and easily achieves low latency as well as high throughput.

The continuous innovation of semiconductor technology enables more complex System on-Chip (SoC) d... more The continuous innovation of semiconductor technology enables more complex System on-Chip (SoC) designs. Tens, even hundreds of intellectual properties (IPs) are integrated into an SoC to provide various functions, including communications, networking, multimedia, storage, etc. The bus scheme connects multiple IP cores with a cost efficient shared medium. The bus-based scheme still fails to satisfy the requirements of future SoC mainly due to two major drawbacks. Non-scalable and the bandwidth is shared by all IPs and thus the bus becomes the performance bottleneck when more and more IPs are connected. In order to interconnect such a high number of elements on a die, researchers have turned to Network On Chip as a replacement to conventional shared buses and ad-hoc wiring solutions. They are attractive due to their regularity and modular design, which can lead to better routability, electrical characteristics and fault tolerance.