Nizar Dahir - Academia.edu (original) (raw)

Papers by Nizar Dahir

Research paper thumbnail of Psoriasis Detection Using Skin Color and Texture Features

Journal of Computer Science, 2010

ABSTRACT Problem statement: In this study a skin disease diagnosis system was developed and teste... more ABSTRACT Problem statement: In this study a skin disease diagnosis system was developed and tested. The system was used for diagnosis of psoriases skin disease. Approach: Present study relied on both skin color and texture features (features derives from the GLCM) to give a better and more efficient recognition accuracy of skin diseases. We used feed forward neural networks to classify input images to be psoriases infected or non psoriasis infected. Results: The system gave very encouraging results during the neural network training and generalization face. Conclusion: The aim of this worked to evaluate the ability of the proposed skin texture recognition algorithm to discriminate between healthy and infected skins and we took the psoriasis disease as example.

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Research paper thumbnail of Minimizing power supply noise through harmonic mappings in networks-on-chip

Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '12, 2012

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Research paper thumbnail of Networks-On-Chip Interconnect Loads Impact on Power Delivery Grid

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Research paper thumbnail of Adaptive Run-Time Thermal Balancing in 3D Network-on-Chip Systems Using Dynamic Programming Networks

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Research paper thumbnail of Highly Adaptive and Deadlock-Free Routing for 3D Networks-on-Chip

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Research paper thumbnail of Deadlock-free and plane-balanced adaptive routing for 3D networks-on-chip

Proceedings of the Fifth International Workshop on Network on Chip Architectures - NoCArc '12, 2012

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Research paper thumbnail of Thermal Optimization in Network-on-Chip-Based 3D Chip Multiprocessors Using Dynamic Programming Networks

ACM Transactions on Embedded Computing Systems, 2014

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Research paper thumbnail of Design and Implementation of Dynamic Thermal-Adaptive Routing Strategy for Networks-on-Chip

2014 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, 2014

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Research paper thumbnail of Hybrid wire-surface wave architecture for one-to-many communication in networks-on-chip

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014, 2014

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Research paper thumbnail of Communication centric on-chip power grid models for networks-on-chip

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

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Research paper thumbnail of Plane-Balanced and Deadlock-Free Adaptive Routing for 3D Networks-on-Chip

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Research paper thumbnail of skin texture recognition using neural networks

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Research paper thumbnail of Highly adaptive and deadlock-free routing for three-dimensional networks-on-chip

IET Computers & Digital Techniques, 2013

ABSTRACT This study proposes a new method for designing adaptive routing algorithms for three-dim... more ABSTRACT This study proposes a new method for designing adaptive routing algorithms for three-dimensional (3D) networks-on-chip (NoCs). This method is based on extending the existing 2D turn model adaptive routing to a 3D scenario. A 3D plane-balanced approach with maximal degree of adaptiveness is achieved by applying a well-defined set of rules for different strata of the 3D NoC. The proposed method is applicable to any of the turn models. In this study, the authors employ odd-even turn model as a basis for introducing the proposed strategy. Experimental results show that the new 3D odd-even turn model can achieve up to 28.5% improvement in performance over conventional 3D odd-even approach. The improvement is consistent for different traffic types and selection strategies. The proposed method enables a new avenue to explore adaptive approaches for future large-scale 3D integration.

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Research paper thumbnail of Modeling and Tools for Power Supply Variations Analysis in Networks-on-Chip

IEEE Transactions on Computers, 2000

ABSTRACT Power supply integrity has become a critical concern with the rapid shrinking feature si... more ABSTRACT Power supply integrity has become a critical concern with the rapid shrinking feature size and the ever increasing power consumption in nanometre scale integration. In particular, on-chip communication in platforms such as networks-on-chip (NoC) dictates the power dissipation and overall system performance in multicore systems and embedded computing architectures. These architectures require a dedicated tool for analyzing the power supply noise which must embed distinctive communication characteristics and spatial parameters. In this paper, we present a tool dedicated to determining the on-chip (VDD)(V_{DD})(VDD) drops due to communication workload in NoCs. This tool integrates a fast power grid model, an NoC simulator, an on-chip link model, and a microarchitectural power model for router. The model has been rigorously verified using SPICE simulations. The proposed model and tools are further exemplified through analyzing the impact of power supply noise for NoC links. Statistical timing analysis of NoC links in the presence of power supply noise was performed to evaluate the bit error rates (BERs). This work would enable better understanding of the tradeoffs existing in the design of NoCs, and the induced power supply noise due to on-chip communication. This understanding is crucial for the analysis of the quality of service (QoS) of communication fabrics in NoCs at the early design stages.

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Research paper thumbnail of Dynamic programming-based runtime thermal management (DPRTM)

ACM Transactions on Design Automation of Electronic Systems, 2013

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Research paper thumbnail of Networks-On-Chip Workload Impact on Power Delivery Grid

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Research paper thumbnail of Psoriasis Detection Using Skin Color and Texture Features

Journal of Computer Science, 2010

ABSTRACT Problem statement: In this study a skin disease diagnosis system was developed and teste... more ABSTRACT Problem statement: In this study a skin disease diagnosis system was developed and tested. The system was used for diagnosis of psoriases skin disease. Approach: Present study relied on both skin color and texture features (features derives from the GLCM) to give a better and more efficient recognition accuracy of skin diseases. We used feed forward neural networks to classify input images to be psoriases infected or non psoriasis infected. Results: The system gave very encouraging results during the neural network training and generalization face. Conclusion: The aim of this worked to evaluate the ability of the proposed skin texture recognition algorithm to discriminate between healthy and infected skins and we took the psoriasis disease as example.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Minimizing power supply noise through harmonic mappings in networks-on-chip

Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '12, 2012

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Research paper thumbnail of Networks-On-Chip Interconnect Loads Impact on Power Delivery Grid

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Adaptive Run-Time Thermal Balancing in 3D Network-on-Chip Systems Using Dynamic Programming Networks

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Highly Adaptive and Deadlock-Free Routing for 3D Networks-on-Chip

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Deadlock-free and plane-balanced adaptive routing for 3D networks-on-chip

Proceedings of the Fifth International Workshop on Network on Chip Architectures - NoCArc '12, 2012

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Thermal Optimization in Network-on-Chip-Based 3D Chip Multiprocessors Using Dynamic Programming Networks

ACM Transactions on Embedded Computing Systems, 2014

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Design and Implementation of Dynamic Thermal-Adaptive Routing Strategy for Networks-on-Chip

2014 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, 2014

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Hybrid wire-surface wave architecture for one-to-many communication in networks-on-chip

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014, 2014

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Communication centric on-chip power grid models for networks-on-chip

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Plane-Balanced and Deadlock-Free Adaptive Routing for 3D Networks-on-Chip

Bookmarks Related papers MentionsView impact

Research paper thumbnail of skin texture recognition using neural networks

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Highly adaptive and deadlock-free routing for three-dimensional networks-on-chip

IET Computers & Digital Techniques, 2013

ABSTRACT This study proposes a new method for designing adaptive routing algorithms for three-dim... more ABSTRACT This study proposes a new method for designing adaptive routing algorithms for three-dimensional (3D) networks-on-chip (NoCs). This method is based on extending the existing 2D turn model adaptive routing to a 3D scenario. A 3D plane-balanced approach with maximal degree of adaptiveness is achieved by applying a well-defined set of rules for different strata of the 3D NoC. The proposed method is applicable to any of the turn models. In this study, the authors employ odd-even turn model as a basis for introducing the proposed strategy. Experimental results show that the new 3D odd-even turn model can achieve up to 28.5% improvement in performance over conventional 3D odd-even approach. The improvement is consistent for different traffic types and selection strategies. The proposed method enables a new avenue to explore adaptive approaches for future large-scale 3D integration.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Modeling and Tools for Power Supply Variations Analysis in Networks-on-Chip

IEEE Transactions on Computers, 2000

ABSTRACT Power supply integrity has become a critical concern with the rapid shrinking feature si... more ABSTRACT Power supply integrity has become a critical concern with the rapid shrinking feature size and the ever increasing power consumption in nanometre scale integration. In particular, on-chip communication in platforms such as networks-on-chip (NoC) dictates the power dissipation and overall system performance in multicore systems and embedded computing architectures. These architectures require a dedicated tool for analyzing the power supply noise which must embed distinctive communication characteristics and spatial parameters. In this paper, we present a tool dedicated to determining the on-chip (VDD)(V_{DD})(VDD) drops due to communication workload in NoCs. This tool integrates a fast power grid model, an NoC simulator, an on-chip link model, and a microarchitectural power model for router. The model has been rigorously verified using SPICE simulations. The proposed model and tools are further exemplified through analyzing the impact of power supply noise for NoC links. Statistical timing analysis of NoC links in the presence of power supply noise was performed to evaluate the bit error rates (BERs). This work would enable better understanding of the tradeoffs existing in the design of NoCs, and the induced power supply noise due to on-chip communication. This understanding is crucial for the analysis of the quality of service (QoS) of communication fabrics in NoCs at the early design stages.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Dynamic programming-based runtime thermal management (DPRTM)

ACM Transactions on Design Automation of Electronic Systems, 2013

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Networks-On-Chip Workload Impact on Power Delivery Grid

Bookmarks Related papers MentionsView impact