PABLO ALEJANDRO FERREYRA - Academia.edu (original) (raw)

Papers by PABLO ALEJANDRO FERREYRA

Research paper thumbnail of OpenCL-Accelerated Simplified General Perturbations 4 Algorithm

The number of space objects such as satellites, spacecraft, and debris are increasing significant... more The number of space objects such as satellites, spacecraft, and debris are increasing significantly, and so is the need for tracking them for security and collision avoidance purposes. In this context, as parallelism is becoming a new paradigm, the need of implementing high performance propagators remain unmet. For this, we implemented Simplified General Perturbations No. 4 (SGP4), a popular analytical orbital propagator, in OpenCL. OpenCL is a rising high performance and heterogeneous computation paradigm aimed to take the best of the processing elements on a given platform, in a parallel fashion, regardless of the underlying architecture. Despite some considerations had to be taken, we prove that our development shows no significant calculation differences, while not only being hardware independent, but also boosting the performance notably by two orders of magnitude in several scenarios.

Research paper thumbnail of Preliminary results of NETFI-2: An automatic method for fault injection on HDL-based designs

2017 18th IEEE Latin American Test Symposium (LATS), 2017

Research paper thumbnail of Delay-Tolerant Wireless Networks on Chip: Preliminary Analysis and Results

2019 IEEE Latin American Test Symposium (LATS), 2019

Delay Tolerant Networks (DTNs) are designed to be robust against delays and disruptions of any ki... more Delay Tolerant Networks (DTNs) are designed to be robust against delays and disruptions of any kind. Indeed, any failure in a set of DTN nodes can be mapped into a delay and thus, can be properly tolerated and counteracted. In general, DTN are applied to scenarios with relative long distances and link interruption between the nodes. In this work, we propose to study DTN operating on distances between nodes several orders of minor magnitude: a wireless DTN on a chip level. The term DTNOC is thus coined to describe DTN applied on a chip scale, where delays and time intervals are reduced accordingly the new application domain. This paper presents the main advantages and characteristics of DTNOCs while discussing up to which point DTNOCs inherit original DTN properties and functions. A preliminary case study is presented and analyzed. Obtained results encourages the future research and development of DTNOCs.

Research paper thumbnail of A Wireless Embedded System for Measuring the Effects of Ionizing Radiations

2019 IEEE Latin American Test Symposium (LATS), 2019

This work presents a new embedded wireless system that allows measuring the effects of ionizing r... more This work presents a new embedded wireless system that allows measuring the effects of ionizing radiation on different electronic devices. The security, reliability and ease of the measurement processes are described by means of an architecture based on wireless monitoring and control fully configurable by the user. All the devices used for the development of the system are low cost and of easy accessibility, such as cell phones or tablets, micro-controllers and Commercial-Off-The-Shelf (COTS) devices. Its application and validation is shown in the study of the counting of singular events in a static RAM exposed to radiation in the TANDAR facility in Buenos Aires, Argentina. Future applications and expected results associated with relevant projects currently underway are also presented.

Research paper thumbnail of LEGv8, Raspberry Pi 3 y una vieja fórmula

Resumen En este trabajo se describe una experiencia sobre la mejora del aprendizaje del Lenguaje ... more Resumen En este trabajo se describe una experiencia sobre la mejora del aprendizaje del Lenguaje Ensamblador (LE) llevada a cabo en la materia Organización del Computador de la Carrera de Licenciatura en Ciencias de la Computación de la Facultad de Matemática, Astronomı́a, Fı́sica y Computación (FAMAF) de la Universidad Nacional de Córdoba (UNC). Los principales objetivos son los de mostrar al alumno la utilidad de adquirir una comprensión de las caracterı́sticas y potencialidades de la programación a nivel de LE, y mostrar la factibilidad de incentivar al alumno en el uso del LE usando las capas bajas de abstracción y en contacto directo con el hardware. El trabajo surge a partir del cambio de arquitectura de conjunto de instrucciones (ISA) estudiadas en la materia. Se pasa de la arquitectura MIPS de 32 bits a la LEGv8 de 64 bits, propuesta en el último libro de Patterson-Hennessy. Se aprovecha el hecho que LEGv8 es un subconjunto propio de ARMv8 y la disponibilidad de plataformas ...

Research paper thumbnail of Internetworking approaches towards along-track segmented satellite architectures

2016 IEEE International Conference on Wireless for Space and Extreme Environments (WiSEE), 2016

The Argentinian Space Agency (CONAE) has been pursuing the development of segmented satellite arc... more The Argentinian Space Agency (CONAE) has been pursuing the development of segmented satellite architectures as a novel strategy to reduce the cost and improve responsiveness of space access. Among the key enablers for these architectures, wireless communication is likely to be the most critical as it requires to operate on a highly dynamic, sparse and extreme environments. In this work, we analyze and derive the main specifications that a communication system for segmented architectures (CSSA) must support. In particular, we provide an abstract model to predict the access time to segmented systems to later propose a layered arrangement of the main specifications for the CSSA. Finally, we analyze by simulation a particular CSSA configuration in a simple yet representative scenario with an along-track flight formation.

Research paper thumbnail of Sistema de comunicación con alta escala de integración, tolerante a fallas, para su utilización en microsatélites

Nuestro grupo esta utilizando dos nuevas tecnicas en el desarrollo electronico aplicado a la inst... more Nuestro grupo esta utilizando dos nuevas tecnicas en el desarrollo electronico aplicado a la instrumentacion cientifica. Una es la del diseno, simulacion y generacion de mascaras de circuitos integrados que seran fabricados en el exterior. Otra, la implementacion de sistemas utilizando Procesadores Digitales de Senales (DSPs). Actualmente se pretende estudiar, desarrollar e implementar dispositivos tolerantes a fallas para comunicaciones en el medio ambiente espacial con tecnologia y presupuesto disponibles en nuestro pais. La importancia del proyecto radica en que nuestra incipiente actividad espacial, necesita de la solucion a los problemas asociados para producir resultados a nivel internacional. (...) Objetivos generales y especificos * Los sistemas de comunicacion con alta escala de integracion, tolerante a fallas, para su utilizacion en microsatelites se perfilan actualmente como la alternativa mas viable para la investigacion y el desarrollo espacial. Esto abre un conjunto de interesantes lineas de trabajo, entre las cuales se encuentra el desarrollo de dispositivos electronicos aptos para soportar las severas condiciones impuestas por el medio ambiente espacial. El uso de elementos de muy alta escala de integracion permite optimizar el aprovechamiento del espacio y potencializar la flexibilidad y perfomance de los sistemas utilizados a bordo. Pero el principal problema que presentan estos sistemas es su vulnerabilidad frente a las radiaciones, que se manifiesta, principalmente, produciendo fallas como "Latch up", corrimientos de voltajes umbrales y S.E.UP S.("Single Event Up Sets"). * Luego, el objetivo especifico consiste en investigar las distintas posibilidades que ofrece el estado actual del arte para mitigar los efectos negativos de estas fallas, estudiar la factibilidad de implementacion de soluciones con la tecnologia y presupuesto disponibles en Argentina, aplicar estos metodos al desarrollo de dispositivos para comunicaciones que utilizan elementos de alta escala de integracion y planear estrategias generales para aplicarlas a otros tipos de dispositivos.

Research paper thumbnail of Desarrollo De Un Sistema Basado en Fpga Para Inyección De Fallas Tipo “Single Event Upset” en Tiempo Real

Research paper thumbnail of OpenCL Overview, Implementation, and Performance Comparison

IEEE Latin America Transactions, 2013

ABSTRACT

Research paper thumbnail of Assessing DTN architecture reliability for distributed satellite constellations: Preliminary results from a case study

2014 IEEE Biennial Congress of Argentina (ARGENCON), 2014

ABSTRACT

Research paper thumbnail of Failure and Coverage Factors Based Markoff Models: A New Approach for Improving the Dependability Estimation in Complex Fault Tolerant Systems Exposed to SEUs

IEEE Transactions on Nuclear Science, 2007

... Pablo A. Ferreyra, Gabriel Viganotti, Carlos A. Marqués, Raoul Velazco, and Ricardo T. Ferrey... more ... Pablo A. Ferreyra, Gabriel Viganotti, Carlos A. Marqués, Raoul Velazco, and Ricardo T. Ferreyra ... R. Velazco is with TIMA LABS, 38031 Grenoble, France (e-mail: raoul.ve-lazco@imag ... The external system takes control of the microprocessor address and data buses and perform ...

Research paper thumbnail of Failure map functions and accelerated mean time to failure tests: new approaches for improving the reliability estimation in systems exposed to single event upsets

IEEE Transactions on Nuclear Science, 2005

Research paper thumbnail of Embedded wireless delay tolerant networks on chips for segmented architectures

International Journal of Embedded Systems, 2021

Research paper thumbnail of Sistema de comunicación con alta escala de integración, tolerante a fallas, para su utilización en microsatélites

Nuestro grupo esta utilizando dos nuevas tecnicas en el desarrollo electronico aplicado a la inst... more Nuestro grupo esta utilizando dos nuevas tecnicas en el desarrollo electronico aplicado a la instrumentacion cientifica. Una es la del diseno, simulacion y generacion de mascaras de circuitos integrados que seran fabricados en el exterior. Otra, la implementacion de sistemas utilizando Procesadores Digitales de Senales (DSPs). Actualmente se pretende estudiar, desarrollar e implementar dispositivos tolerantes a fallas para comunicaciones en el medio ambiente espacial con tecnologia y presupuesto disponibles en nuestro pais. La importancia del proyecto radica en que nuestra incipiente actividad espacial, necesita de la solucion a los problemas asociados para producir resultados a nivel internacional. (...) Objetivos generales y especificos * Los sistemas de comunicacion con alta escala de integracion, tolerante a fallas, para su utilizacion en microsatelites se perfilan actualmente como la alternativa mas viable para la investigacion y el desarrollo espacial. Esto abre un conjunto de interesantes lineas de trabajo, entre las cuales se encuentra el desarrollo de dispositivos electronicos aptos para soportar las severas condiciones impuestas por el medio ambiente espacial. El uso de elementos de muy alta escala de integracion permite optimizar el aprovechamiento del espacio y potencializar la flexibilidad y perfomance de los sistemas utilizados a bordo. Pero el principal problema que presentan estos sistemas es su vulnerabilidad frente a las radiaciones, que se manifiesta, principalmente, produciendo fallas como "Latch up", corrimientos de voltajes umbrales y S.E.UP S.("Single Event Up Sets"). * Luego, el objetivo especifico consiste en investigar las distintas posibilidades que ofrece el estado actual del arte para mitigar los efectos negativos de estas fallas, estudiar la factibilidad de implementacion de soluciones con la tecnologia y presupuesto disponibles en Argentina, aplicar estos metodos al desarrollo de dispositivos para comunicaciones que utilizan elementos de alta escala de integracion y planear estrategias generales para aplicarlas a otros tipos de dispositivos.

Research paper thumbnail of Assessing DTN architecture reliability for distributed satellite constellations: Preliminary results from a case study

2014 IEEE Biennial Congress of Argentina (ARGENCON), 2014

ABSTRACT

Research paper thumbnail of Desarrollo De Un Sistema Basado en Fpga Para Inyección De Fallas Tipo “Single Event Upset” en Tiempo Real

Research paper thumbnail of Internetworking approaches towards along-track segmented satellite architectures

The Argentinian Space Agency (CONAE) has been pursuing the development of segmented satellite arc... more The Argentinian Space Agency (CONAE) has been pursuing the development of segmented satellite architectures as a novel strategy to reduce the cost and improve responsiveness of space access. Among the key enablers for these architectures, wireless communication is likely to be the most critical as it requires to operate on a highly dynamic, sparse and extreme environments. In this work, we analyze and derive the main specifications that a communication system for segmented architectures (CSSA) must support. In particular, we provide an abstract model to predict the access time to segmented systems to later propose a layered arrangement of the main specifications for the CSSA. Finally, we analyze by simulation a particular CSSA configuration in a simple yet representative scenario with an along-track flight formation.

Research paper thumbnail of Injecting single event upsets in a digital signal processor by means of direct memory access requests: a new method for generating bit flips

In this paper a novel approach for injecting Single Event Upsets, (SEU), by means of direct memor... more In this paper a novel approach for injecting Single Event Upsets, (SEU), by means of direct memory access, (DMA), mechanisms is presented. The system consists in a PC based control unit that generates DMA requests randomly in time to a board containing the processor under test, and a test unit. Experimentation performed on a digital signal processor intended to be used in a satellite project illustrates the potentialities of the proposed approach.

Research paper thumbnail of Failure map functions and accelerated MTTF tests: now approaches for improving the reliability estimation in systems exposed to seus

Reliability prediction in digital systems exposed to Single Event Upsets (SEW is a central aspect... more Reliability prediction in digital systems exposed to Single Event Upsets (SEW is a central aspect in the development of fault tolerant computers devoted to operate in radioactive environment (space, nuclear plants) and, with the miniaturization, becomes a concern€ or ...

Research paper thumbnail of Injecting bit flip faults by means of a purely software approach: a case studied

Bit flips provoked by radiation are a main concern for space applications. A fault injection expe... more Bit flips provoked by radiation are a main concern for space applications. A fault injection experiment performed using a software simulator is described in this paper. Obtained results allow to predict a low sensitivity to soft errors for the studied application, putting in evidence critical memory elements.

Research paper thumbnail of OpenCL-Accelerated Simplified General Perturbations 4 Algorithm

The number of space objects such as satellites, spacecraft, and debris are increasing significant... more The number of space objects such as satellites, spacecraft, and debris are increasing significantly, and so is the need for tracking them for security and collision avoidance purposes. In this context, as parallelism is becoming a new paradigm, the need of implementing high performance propagators remain unmet. For this, we implemented Simplified General Perturbations No. 4 (SGP4), a popular analytical orbital propagator, in OpenCL. OpenCL is a rising high performance and heterogeneous computation paradigm aimed to take the best of the processing elements on a given platform, in a parallel fashion, regardless of the underlying architecture. Despite some considerations had to be taken, we prove that our development shows no significant calculation differences, while not only being hardware independent, but also boosting the performance notably by two orders of magnitude in several scenarios.

Research paper thumbnail of Preliminary results of NETFI-2: An automatic method for fault injection on HDL-based designs

2017 18th IEEE Latin American Test Symposium (LATS), 2017

Research paper thumbnail of Delay-Tolerant Wireless Networks on Chip: Preliminary Analysis and Results

2019 IEEE Latin American Test Symposium (LATS), 2019

Delay Tolerant Networks (DTNs) are designed to be robust against delays and disruptions of any ki... more Delay Tolerant Networks (DTNs) are designed to be robust against delays and disruptions of any kind. Indeed, any failure in a set of DTN nodes can be mapped into a delay and thus, can be properly tolerated and counteracted. In general, DTN are applied to scenarios with relative long distances and link interruption between the nodes. In this work, we propose to study DTN operating on distances between nodes several orders of minor magnitude: a wireless DTN on a chip level. The term DTNOC is thus coined to describe DTN applied on a chip scale, where delays and time intervals are reduced accordingly the new application domain. This paper presents the main advantages and characteristics of DTNOCs while discussing up to which point DTNOCs inherit original DTN properties and functions. A preliminary case study is presented and analyzed. Obtained results encourages the future research and development of DTNOCs.

Research paper thumbnail of A Wireless Embedded System for Measuring the Effects of Ionizing Radiations

2019 IEEE Latin American Test Symposium (LATS), 2019

This work presents a new embedded wireless system that allows measuring the effects of ionizing r... more This work presents a new embedded wireless system that allows measuring the effects of ionizing radiation on different electronic devices. The security, reliability and ease of the measurement processes are described by means of an architecture based on wireless monitoring and control fully configurable by the user. All the devices used for the development of the system are low cost and of easy accessibility, such as cell phones or tablets, micro-controllers and Commercial-Off-The-Shelf (COTS) devices. Its application and validation is shown in the study of the counting of singular events in a static RAM exposed to radiation in the TANDAR facility in Buenos Aires, Argentina. Future applications and expected results associated with relevant projects currently underway are also presented.

Research paper thumbnail of LEGv8, Raspberry Pi 3 y una vieja fórmula

Resumen En este trabajo se describe una experiencia sobre la mejora del aprendizaje del Lenguaje ... more Resumen En este trabajo se describe una experiencia sobre la mejora del aprendizaje del Lenguaje Ensamblador (LE) llevada a cabo en la materia Organización del Computador de la Carrera de Licenciatura en Ciencias de la Computación de la Facultad de Matemática, Astronomı́a, Fı́sica y Computación (FAMAF) de la Universidad Nacional de Córdoba (UNC). Los principales objetivos son los de mostrar al alumno la utilidad de adquirir una comprensión de las caracterı́sticas y potencialidades de la programación a nivel de LE, y mostrar la factibilidad de incentivar al alumno en el uso del LE usando las capas bajas de abstracción y en contacto directo con el hardware. El trabajo surge a partir del cambio de arquitectura de conjunto de instrucciones (ISA) estudiadas en la materia. Se pasa de la arquitectura MIPS de 32 bits a la LEGv8 de 64 bits, propuesta en el último libro de Patterson-Hennessy. Se aprovecha el hecho que LEGv8 es un subconjunto propio de ARMv8 y la disponibilidad de plataformas ...

Research paper thumbnail of Internetworking approaches towards along-track segmented satellite architectures

2016 IEEE International Conference on Wireless for Space and Extreme Environments (WiSEE), 2016

The Argentinian Space Agency (CONAE) has been pursuing the development of segmented satellite arc... more The Argentinian Space Agency (CONAE) has been pursuing the development of segmented satellite architectures as a novel strategy to reduce the cost and improve responsiveness of space access. Among the key enablers for these architectures, wireless communication is likely to be the most critical as it requires to operate on a highly dynamic, sparse and extreme environments. In this work, we analyze and derive the main specifications that a communication system for segmented architectures (CSSA) must support. In particular, we provide an abstract model to predict the access time to segmented systems to later propose a layered arrangement of the main specifications for the CSSA. Finally, we analyze by simulation a particular CSSA configuration in a simple yet representative scenario with an along-track flight formation.

Research paper thumbnail of Sistema de comunicación con alta escala de integración, tolerante a fallas, para su utilización en microsatélites

Nuestro grupo esta utilizando dos nuevas tecnicas en el desarrollo electronico aplicado a la inst... more Nuestro grupo esta utilizando dos nuevas tecnicas en el desarrollo electronico aplicado a la instrumentacion cientifica. Una es la del diseno, simulacion y generacion de mascaras de circuitos integrados que seran fabricados en el exterior. Otra, la implementacion de sistemas utilizando Procesadores Digitales de Senales (DSPs). Actualmente se pretende estudiar, desarrollar e implementar dispositivos tolerantes a fallas para comunicaciones en el medio ambiente espacial con tecnologia y presupuesto disponibles en nuestro pais. La importancia del proyecto radica en que nuestra incipiente actividad espacial, necesita de la solucion a los problemas asociados para producir resultados a nivel internacional. (...) Objetivos generales y especificos * Los sistemas de comunicacion con alta escala de integracion, tolerante a fallas, para su utilizacion en microsatelites se perfilan actualmente como la alternativa mas viable para la investigacion y el desarrollo espacial. Esto abre un conjunto de interesantes lineas de trabajo, entre las cuales se encuentra el desarrollo de dispositivos electronicos aptos para soportar las severas condiciones impuestas por el medio ambiente espacial. El uso de elementos de muy alta escala de integracion permite optimizar el aprovechamiento del espacio y potencializar la flexibilidad y perfomance de los sistemas utilizados a bordo. Pero el principal problema que presentan estos sistemas es su vulnerabilidad frente a las radiaciones, que se manifiesta, principalmente, produciendo fallas como "Latch up", corrimientos de voltajes umbrales y S.E.UP S.("Single Event Up Sets"). * Luego, el objetivo especifico consiste en investigar las distintas posibilidades que ofrece el estado actual del arte para mitigar los efectos negativos de estas fallas, estudiar la factibilidad de implementacion de soluciones con la tecnologia y presupuesto disponibles en Argentina, aplicar estos metodos al desarrollo de dispositivos para comunicaciones que utilizan elementos de alta escala de integracion y planear estrategias generales para aplicarlas a otros tipos de dispositivos.

Research paper thumbnail of Desarrollo De Un Sistema Basado en Fpga Para Inyección De Fallas Tipo “Single Event Upset” en Tiempo Real

Research paper thumbnail of OpenCL Overview, Implementation, and Performance Comparison

IEEE Latin America Transactions, 2013

ABSTRACT

Research paper thumbnail of Assessing DTN architecture reliability for distributed satellite constellations: Preliminary results from a case study

2014 IEEE Biennial Congress of Argentina (ARGENCON), 2014

ABSTRACT

Research paper thumbnail of Failure and Coverage Factors Based Markoff Models: A New Approach for Improving the Dependability Estimation in Complex Fault Tolerant Systems Exposed to SEUs

IEEE Transactions on Nuclear Science, 2007

... Pablo A. Ferreyra, Gabriel Viganotti, Carlos A. Marqués, Raoul Velazco, and Ricardo T. Ferrey... more ... Pablo A. Ferreyra, Gabriel Viganotti, Carlos A. Marqués, Raoul Velazco, and Ricardo T. Ferreyra ... R. Velazco is with TIMA LABS, 38031 Grenoble, France (e-mail: raoul.ve-lazco@imag ... The external system takes control of the microprocessor address and data buses and perform ...

Research paper thumbnail of Failure map functions and accelerated mean time to failure tests: new approaches for improving the reliability estimation in systems exposed to single event upsets

IEEE Transactions on Nuclear Science, 2005

Research paper thumbnail of Embedded wireless delay tolerant networks on chips for segmented architectures

International Journal of Embedded Systems, 2021

Research paper thumbnail of Sistema de comunicación con alta escala de integración, tolerante a fallas, para su utilización en microsatélites

Nuestro grupo esta utilizando dos nuevas tecnicas en el desarrollo electronico aplicado a la inst... more Nuestro grupo esta utilizando dos nuevas tecnicas en el desarrollo electronico aplicado a la instrumentacion cientifica. Una es la del diseno, simulacion y generacion de mascaras de circuitos integrados que seran fabricados en el exterior. Otra, la implementacion de sistemas utilizando Procesadores Digitales de Senales (DSPs). Actualmente se pretende estudiar, desarrollar e implementar dispositivos tolerantes a fallas para comunicaciones en el medio ambiente espacial con tecnologia y presupuesto disponibles en nuestro pais. La importancia del proyecto radica en que nuestra incipiente actividad espacial, necesita de la solucion a los problemas asociados para producir resultados a nivel internacional. (...) Objetivos generales y especificos * Los sistemas de comunicacion con alta escala de integracion, tolerante a fallas, para su utilizacion en microsatelites se perfilan actualmente como la alternativa mas viable para la investigacion y el desarrollo espacial. Esto abre un conjunto de interesantes lineas de trabajo, entre las cuales se encuentra el desarrollo de dispositivos electronicos aptos para soportar las severas condiciones impuestas por el medio ambiente espacial. El uso de elementos de muy alta escala de integracion permite optimizar el aprovechamiento del espacio y potencializar la flexibilidad y perfomance de los sistemas utilizados a bordo. Pero el principal problema que presentan estos sistemas es su vulnerabilidad frente a las radiaciones, que se manifiesta, principalmente, produciendo fallas como "Latch up", corrimientos de voltajes umbrales y S.E.UP S.("Single Event Up Sets"). * Luego, el objetivo especifico consiste en investigar las distintas posibilidades que ofrece el estado actual del arte para mitigar los efectos negativos de estas fallas, estudiar la factibilidad de implementacion de soluciones con la tecnologia y presupuesto disponibles en Argentina, aplicar estos metodos al desarrollo de dispositivos para comunicaciones que utilizan elementos de alta escala de integracion y planear estrategias generales para aplicarlas a otros tipos de dispositivos.

Research paper thumbnail of Assessing DTN architecture reliability for distributed satellite constellations: Preliminary results from a case study

2014 IEEE Biennial Congress of Argentina (ARGENCON), 2014

ABSTRACT

Research paper thumbnail of Desarrollo De Un Sistema Basado en Fpga Para Inyección De Fallas Tipo “Single Event Upset” en Tiempo Real

Research paper thumbnail of Internetworking approaches towards along-track segmented satellite architectures

The Argentinian Space Agency (CONAE) has been pursuing the development of segmented satellite arc... more The Argentinian Space Agency (CONAE) has been pursuing the development of segmented satellite architectures as a novel strategy to reduce the cost and improve responsiveness of space access. Among the key enablers for these architectures, wireless communication is likely to be the most critical as it requires to operate on a highly dynamic, sparse and extreme environments. In this work, we analyze and derive the main specifications that a communication system for segmented architectures (CSSA) must support. In particular, we provide an abstract model to predict the access time to segmented systems to later propose a layered arrangement of the main specifications for the CSSA. Finally, we analyze by simulation a particular CSSA configuration in a simple yet representative scenario with an along-track flight formation.

Research paper thumbnail of Injecting single event upsets in a digital signal processor by means of direct memory access requests: a new method for generating bit flips

In this paper a novel approach for injecting Single Event Upsets, (SEU), by means of direct memor... more In this paper a novel approach for injecting Single Event Upsets, (SEU), by means of direct memory access, (DMA), mechanisms is presented. The system consists in a PC based control unit that generates DMA requests randomly in time to a board containing the processor under test, and a test unit. Experimentation performed on a digital signal processor intended to be used in a satellite project illustrates the potentialities of the proposed approach.

Research paper thumbnail of Failure map functions and accelerated MTTF tests: now approaches for improving the reliability estimation in systems exposed to seus

Reliability prediction in digital systems exposed to Single Event Upsets (SEW is a central aspect... more Reliability prediction in digital systems exposed to Single Event Upsets (SEW is a central aspect in the development of fault tolerant computers devoted to operate in radioactive environment (space, nuclear plants) and, with the miniaturization, becomes a concern€ or ...

Research paper thumbnail of Injecting bit flip faults by means of a purely software approach: a case studied

Bit flips provoked by radiation are a main concern for space applications. A fault injection expe... more Bit flips provoked by radiation are a main concern for space applications. A fault injection experiment performed using a software simulator is described in this paper. Obtained results allow to predict a low sensitivity to soft errors for the studied application, putting in evidence critical memory elements.