PIYAS SAMANTA - Academia.edu (original) (raw)
Papers by PIYAS SAMANTA
1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings
oxide-silicon (MOS) device degradation due to trapping of positive charges in thin (27, 33 nm) Si... more oxide-silicon (MOS) device degradation due to trapping of positive charges in thin (27, 33 nm) Si02 gate oxides is presented. n+-polySi-gate (MOS) capacitors are stressed at a low electron injection fluence (<O.OI C/cm2) by Fowler-Nordheim (FN) electron tunneling &om the quantized accumulation layer of (100) n-Si substrate, at constant current and constant applied gate voltage. The present analysis assumes tunneling electron initiated band-lo-band impact ionization (BTBII) in SiO2, as the possible source of trapped holes during stress. The validity of the present analysis has been examined by comparing the theoretical values with the experhental data of FN threshold voltage shift AVFN of Fazan et al.
Journal of Applied Physics, 2017
We present a detailed investigation on temperature-dependent current conduction through thin tunn... more We present a detailed investigation on temperature-dependent current conduction through thin tunnel oxides grown on degenerately doped n-type silicon (n þ-Si) under positive bias (V G) on heavily doped n-type polycrystalline silicon (n þ-polySi) gate in metal-oxide-semiconductor devices. The leakage current measured between 298 and 573 K and at oxide fields ranging from 6 to 10 MV/cm is primarily attributed to Poole-Frenkel (PF) emission of trapped electrons from the neutral electron traps located in the silicon dioxide (SiO 2) band gap in addition to Fowler-Nordheim (FN) tunneling of electrons from n þ-Si acting as the drain node in FLOating gate Tunnel OXide Electrically Erasable Programmable Read-Only Memory devices. Process-induced neutral electron traps are located at 0.18 eV and 0.9 eV below the SiO 2 conduction band. Throughout the temperature range studied here, PF emission current I PF dominates FN electron tunneling current I FN at oxide electric fields E ox between 6 and 10 MV/cm. A physics based new analytical formula has been developed for FN tunneling of electrons from the accumulation layer of degenerate semiconductors at a wide range of temperatures incorporating the image force barrier rounding effect. FN tunneling has been formulated in the framework of Wentzel-Kramers-Brilloiun taking into account the correction factor due to abrupt variation of the energy barrier at the cathode/oxide interface. The effect of interfacial and near-interfacial trapped-oxide charges on FN tunneling has also been investigated in detail at positive V G. The mechanism of leakage current conduction through SiO 2 films plays a crucial role in simulation of time-dependent dielectric breakdown of the memory devices and to precisely predict the normal operating field or applied floating gate (FG) voltage for lifetime projection of the devices. In addition, we present theoretical results showing the effect of drain doping concentration on the FG leakage current.
Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena, 2017
Journal of Applied Physics, 2016
Articles you may be interested in Leakage current conduction, hole injection, and time-dependent ... more Articles you may be interested in Leakage current conduction, hole injection, and time-dependent dielectric breakdown of n-4H-SiC MOS capacitors during positive bias temperature stress
National Radio Science Conference, Mar 15, 2005
A simulator has been developed to predict the gate oxide breakdown in metal-oxidesilicon (MUS) de... more A simulator has been developed to predict the gate oxide breakdown in metal-oxidesilicon (MUS) devices under high-field Fowler-Nordheim (FN) stress with positive bias on the polycrystalline silicon gate. Our simulator takes into account hole trapping and positive charge generation due to trap-to-band ionization in thick to thin (33-8nm) thermally grown silicon dioxide (SiO$films.
1996 International Semiconductor Conference. 19th Edition. CAS'96 Proceedings
Metal-Oxide-Silicon (MOS) device degradation due to trapped holes in the bulk of thin SiO/sub 2/ ... more Metal-Oxide-Silicon (MOS) device degradation due to trapped holes in the bulk of thin SiO/sub 2/ (22-33 nm) gate oxide during low fluence Fowler-Nordheim (FN) injection from the accumulated <100> n-Si of n/sup +/ polySi gate MOS capacitors has been theoretically modeled. The model is based on tunneling electron initiated band-to-band impact ionization (BTBII) as the possible source of generated holes. The validity of the present analysis has been compared with the experimental data of FN voltage shift /spl Delta/V/sub FN/ of Fazan et al. A comparative study of degradation during constant current and voltage FN stress is also presented.
Extended Abstracts of the 2008 International Conference on Solid State Devices and Materials, 2008
2014 IEEE International Conference on Electron Devices and Solid-State Circuits, 2014
A detailed investigation of the effect of nitridation of hafnium silicate on positive bias temper... more A detailed investigation of the effect of nitridation of hafnium silicate on positive bias temperature instability (PBTI) in n+-polySi gate pMOS capacitor structures has been presented. Our analysis shows that nitridation improves the intrinsic oxide breakdown field, reduces the equivalent oxide thickness (EOT) and as-grown surface state density Dit by an order of magnitude. On the other hand, like NBTI degradation, nitridation significantly enhances PBTI degradation in pMOS devices causing reduction in PBTI lifetime at a given applied voltage VG. However, both nitrided and non-nitrided gate stacks reaches 10 year lifetime at an applied gate bias of 1.2 V.
2014 IEEE International Conference on Electron Devices and Solid-State Circuits, 2014
For the first time, an experimental investigation of dopant passivation/depassivation in the sili... more For the first time, an experimental investigation of dopant passivation/depassivation in the silicon substrate of metal-oxide-semiconductor (MOS) devices is presented during and after negative bias temperature stress (NBTS). It is believed that dopant passivation/depassivation is caused by hydrogen diffusion into the substrate forming complex with the dopant during NBTS and back diffusion of hydrogen from the passivated dopant atom during relaxation phase, respectively. The source of the diffusing hydrogen species responsible for dopant passivation during NBTS is the atomic hydrogen (Ho) liberated during interface state (Nit) generation by the hot electron impact with the Si3 ≡ SiH bonds at the Si/SiO2 interface. Dopant passivation mechanism significantly contributes in the measured threshold and flatband voltage shifts ΔVT and ΔVfb, respectively during NBTS. We propose that the experimentally observed new degradation phenomena should be taken into account in evaluation of the NBTI induced oxide charge trapping and interface trap creation.
Gate oxide degradation has been theoretically investigated in n/sup +/-polySi-gate metal-oxide-se... more Gate oxide degradation has been theoretically investigated in n/sup +/-polySi-gate metal-oxide-semiconductor (MOS) capacitors during low fluence (/spl les/0.01 C/cm/sup 2/) Fowler-Nordheim (FN) injection from (100) n-Si at a wide range (6-12 MV/cm) of oxide electric field. Oxide thicknesses were 22, 27 and 33 nm. Trapped positive charge induced oxide degradation is modeled with a new coupled trapping dynamics based on tunneling electron initiated band to band impact ionization (BTBI) and trap ionization (TTBI) in the oxide gap. In addition, we have compared the degradation during and FN stress at constant current and constant gate voltage.
2009 2nd International Workshop on Electron Devices and Semiconductor Technology, 2009
An experimental investigation on oxide positive charge buildup in sub 3-nm silicon dioxide (SiO2)... more An experimental investigation on oxide positive charge buildup in sub 3-nm silicon dioxide (SiO2) films is presented during direct tunneling (DT) of electrons at -1.8 V of gate bias. The measurement results can be best explained by hole generation via anode hole injection (AHI) mechanism and the subsequent trapping of holes in the as-fabricated neutral hole traps in the oxide.
2007 International Workshop on Physics of Semiconductor Devices, 2007
Electrical characteristics of hafnium oxide (HfO2)/silicon dioxide (SiO2) gate dielectric stack d... more Electrical characteristics of hafnium oxide (HfO2)/silicon dioxide (SiO2) gate dielectric stack during both constant voltage stress (CVS) and constant current stress (CCS) have been experimentally investigated with varying thickness of the HfO2 layer. The generation kinetics of bulk, interface and border trapped charges have been discussed showing a correlation among them. Nature of intrinsic hole traps in SiO2 has also been studied from an independent charge relaxation experiment. In addition, time-dependent dielectric breakdown (TDDB) has been studied during CVS.
Physica Status Solidi (a), 1995
... 0.5 PIYAS SAMANTA and CK SARKAR I ... In order to quantitatively understand the trapping beha... more ... 0.5 PIYAS SAMANTA and CK SARKAR I ... In order to quantitatively understand the trapping behaviorde-pendence on the injection techniques, we have used the value of the initial constant, applied field E,, equal to the value of the cathode field E, during constant current stress. ...
Solid-State Electronics, 2002
A theoretical investigation on the gate polarity dependence of Fowler–Nordheim (FN) tunneling ele... more A theoretical investigation on the gate polarity dependence of Fowler–Nordheim (FN) tunneling electron initiated impact ionization probabilities in the bulk silicon dioxide (SiO2) films as well as hole injection from the anode material (n+ poly-Si gate or silicon substrate) in metal-oxide-silicon devices is presented. Our theoretical results of the gate polarity dependence of the probabilities of various impact ionization processes
Semiconductor Science and Technology, 2006
A comprehensive analysis of the stress-induced leakage current (SILC) through thermally grown ult... more A comprehensive analysis of the stress-induced leakage current (SILC) through thermally grown ultrathin silicon dioxide (SiO2) films has been presented based on experimental observations. Stressing and sensing measurements are done in tantalum nitride (TaN) gate metal-oxide-silicon (MOS) capacitors at negative gate bias in the direct tunnelling (DT) regime. Both transient and steady-state DT SILCs have been studied in oxides with
Semiconductor Science and Technology, 1996
... current stress Piyas Samanta† and CK Sarkar‡ † Department of Physics, Jadavpur University, Ca... more ... current stress Piyas Samanta† and CK Sarkar‡ † Department of Physics, Jadavpur University, Calcutta 32, India ‡ Department of Electronics & Telecommunication Engineering, Jadavpur University, Calcutta 32, India ... σr〉 = ∫ Ea Ec σr(E)dE /∫ Ea ...
Microelectronics Reliability, 2010
We compare charge carrier generation/trapping related degradation in control oxide (SiO 2) and Hf... more We compare charge carrier generation/trapping related degradation in control oxide (SiO 2) and HfO 2 /SiO 2 stack of an identical equivalent-oxide-thickness (EOT) during constant gate voltage stress of n-type metal-oxide-semiconductor (nMOS) capacitors. Irrespective of these two dielectrics, the kinetics of generation of both surface states and oxide-trapped positive charges are found to be similar. Our analysis shows that the positive oxide charge buildup during CVS is due to trapping of protons by the strained SiAOASi bonds in either of the devices. We demonstrate that compared to SiO 2 devices, HfO 2 devices with an equal EOT better perform in CMOS logic applications. On the other hand, our results indicate that the control oxide is better in charge trapping memory devices. Furthermore, the lifetime of the control oxide devices is observed longer than that of HfO 2 devices at a given operating voltage.
Microelectronic Engineering, 2007
We have investigated electrical stress-induced charge carrier generation/trapping in a 4.2 nm thi... more We have investigated electrical stress-induced charge carrier generation/trapping in a 4.2 nm thick (physical thickness T phy) hafnium oxide (HfO 2)/silicon dioxide (SiO 2) dielectric stack in metal-oxide-semiconductor (MOS) capacitor structures with negative bias on the gate. It is found that electron trapping is suppressed in our devices having an equivalent oxide thickness (EOT) as low as 2.4 nm. Our measurement results indicate that proton-induced defect generation is the dominant mechanism of generation of bulk, border and interface traps during stress. In addition, we have shown that constant voltage stress (CVS) degrades the dielectric quality more than constant current stress (CCS).
![Research paper thumbnail of Charge Trapping Related Degradation of Thin HfAlO∕SiO[sub 2] Gate Dielectric Stack during Constant-Voltage Stress](https://attachments.academia-assets.com/99563047/thumbnails/1.jpg)
](Journal of The Electrochemical Society, 2009
[Journal of The Electrochemical Society 156, H661 (2009)]. Piyas Samanta, Chin-Lung Cheng, Yao-Je... more [Journal of The Electrochemical Society 156, H661 (2009)]. Piyas Samanta, Chin-Lung Cheng, Yao-Jen Lee. Abstract. ... Acknowledgment. PS thanks Dr. Souvik Mahapatra at Microelectronics Division, IIT, Bombay, for providing the measurement facilities. ...
1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings
oxide-silicon (MOS) device degradation due to trapping of positive charges in thin (27, 33 nm) Si... more oxide-silicon (MOS) device degradation due to trapping of positive charges in thin (27, 33 nm) Si02 gate oxides is presented. n+-polySi-gate (MOS) capacitors are stressed at a low electron injection fluence (<O.OI C/cm2) by Fowler-Nordheim (FN) electron tunneling &om the quantized accumulation layer of (100) n-Si substrate, at constant current and constant applied gate voltage. The present analysis assumes tunneling electron initiated band-lo-band impact ionization (BTBII) in SiO2, as the possible source of trapped holes during stress. The validity of the present analysis has been examined by comparing the theoretical values with the experhental data of FN threshold voltage shift AVFN of Fazan et al.
Journal of Applied Physics, 2017
We present a detailed investigation on temperature-dependent current conduction through thin tunn... more We present a detailed investigation on temperature-dependent current conduction through thin tunnel oxides grown on degenerately doped n-type silicon (n þ-Si) under positive bias (V G) on heavily doped n-type polycrystalline silicon (n þ-polySi) gate in metal-oxide-semiconductor devices. The leakage current measured between 298 and 573 K and at oxide fields ranging from 6 to 10 MV/cm is primarily attributed to Poole-Frenkel (PF) emission of trapped electrons from the neutral electron traps located in the silicon dioxide (SiO 2) band gap in addition to Fowler-Nordheim (FN) tunneling of electrons from n þ-Si acting as the drain node in FLOating gate Tunnel OXide Electrically Erasable Programmable Read-Only Memory devices. Process-induced neutral electron traps are located at 0.18 eV and 0.9 eV below the SiO 2 conduction band. Throughout the temperature range studied here, PF emission current I PF dominates FN electron tunneling current I FN at oxide electric fields E ox between 6 and 10 MV/cm. A physics based new analytical formula has been developed for FN tunneling of electrons from the accumulation layer of degenerate semiconductors at a wide range of temperatures incorporating the image force barrier rounding effect. FN tunneling has been formulated in the framework of Wentzel-Kramers-Brilloiun taking into account the correction factor due to abrupt variation of the energy barrier at the cathode/oxide interface. The effect of interfacial and near-interfacial trapped-oxide charges on FN tunneling has also been investigated in detail at positive V G. The mechanism of leakage current conduction through SiO 2 films plays a crucial role in simulation of time-dependent dielectric breakdown of the memory devices and to precisely predict the normal operating field or applied floating gate (FG) voltage for lifetime projection of the devices. In addition, we present theoretical results showing the effect of drain doping concentration on the FG leakage current.
Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena, 2017
Journal of Applied Physics, 2016
Articles you may be interested in Leakage current conduction, hole injection, and time-dependent ... more Articles you may be interested in Leakage current conduction, hole injection, and time-dependent dielectric breakdown of n-4H-SiC MOS capacitors during positive bias temperature stress
National Radio Science Conference, Mar 15, 2005
A simulator has been developed to predict the gate oxide breakdown in metal-oxidesilicon (MUS) de... more A simulator has been developed to predict the gate oxide breakdown in metal-oxidesilicon (MUS) devices under high-field Fowler-Nordheim (FN) stress with positive bias on the polycrystalline silicon gate. Our simulator takes into account hole trapping and positive charge generation due to trap-to-band ionization in thick to thin (33-8nm) thermally grown silicon dioxide (SiO$films.
1996 International Semiconductor Conference. 19th Edition. CAS'96 Proceedings
Metal-Oxide-Silicon (MOS) device degradation due to trapped holes in the bulk of thin SiO/sub 2/ ... more Metal-Oxide-Silicon (MOS) device degradation due to trapped holes in the bulk of thin SiO/sub 2/ (22-33 nm) gate oxide during low fluence Fowler-Nordheim (FN) injection from the accumulated <100> n-Si of n/sup +/ polySi gate MOS capacitors has been theoretically modeled. The model is based on tunneling electron initiated band-to-band impact ionization (BTBII) as the possible source of generated holes. The validity of the present analysis has been compared with the experimental data of FN voltage shift /spl Delta/V/sub FN/ of Fazan et al. A comparative study of degradation during constant current and voltage FN stress is also presented.
Extended Abstracts of the 2008 International Conference on Solid State Devices and Materials, 2008
2014 IEEE International Conference on Electron Devices and Solid-State Circuits, 2014
A detailed investigation of the effect of nitridation of hafnium silicate on positive bias temper... more A detailed investigation of the effect of nitridation of hafnium silicate on positive bias temperature instability (PBTI) in n+-polySi gate pMOS capacitor structures has been presented. Our analysis shows that nitridation improves the intrinsic oxide breakdown field, reduces the equivalent oxide thickness (EOT) and as-grown surface state density Dit by an order of magnitude. On the other hand, like NBTI degradation, nitridation significantly enhances PBTI degradation in pMOS devices causing reduction in PBTI lifetime at a given applied voltage VG. However, both nitrided and non-nitrided gate stacks reaches 10 year lifetime at an applied gate bias of 1.2 V.
2014 IEEE International Conference on Electron Devices and Solid-State Circuits, 2014
For the first time, an experimental investigation of dopant passivation/depassivation in the sili... more For the first time, an experimental investigation of dopant passivation/depassivation in the silicon substrate of metal-oxide-semiconductor (MOS) devices is presented during and after negative bias temperature stress (NBTS). It is believed that dopant passivation/depassivation is caused by hydrogen diffusion into the substrate forming complex with the dopant during NBTS and back diffusion of hydrogen from the passivated dopant atom during relaxation phase, respectively. The source of the diffusing hydrogen species responsible for dopant passivation during NBTS is the atomic hydrogen (Ho) liberated during interface state (Nit) generation by the hot electron impact with the Si3 ≡ SiH bonds at the Si/SiO2 interface. Dopant passivation mechanism significantly contributes in the measured threshold and flatband voltage shifts ΔVT and ΔVfb, respectively during NBTS. We propose that the experimentally observed new degradation phenomena should be taken into account in evaluation of the NBTI induced oxide charge trapping and interface trap creation.
Gate oxide degradation has been theoretically investigated in n/sup +/-polySi-gate metal-oxide-se... more Gate oxide degradation has been theoretically investigated in n/sup +/-polySi-gate metal-oxide-semiconductor (MOS) capacitors during low fluence (/spl les/0.01 C/cm/sup 2/) Fowler-Nordheim (FN) injection from (100) n-Si at a wide range (6-12 MV/cm) of oxide electric field. Oxide thicknesses were 22, 27 and 33 nm. Trapped positive charge induced oxide degradation is modeled with a new coupled trapping dynamics based on tunneling electron initiated band to band impact ionization (BTBI) and trap ionization (TTBI) in the oxide gap. In addition, we have compared the degradation during and FN stress at constant current and constant gate voltage.
2009 2nd International Workshop on Electron Devices and Semiconductor Technology, 2009
An experimental investigation on oxide positive charge buildup in sub 3-nm silicon dioxide (SiO2)... more An experimental investigation on oxide positive charge buildup in sub 3-nm silicon dioxide (SiO2) films is presented during direct tunneling (DT) of electrons at -1.8 V of gate bias. The measurement results can be best explained by hole generation via anode hole injection (AHI) mechanism and the subsequent trapping of holes in the as-fabricated neutral hole traps in the oxide.
2007 International Workshop on Physics of Semiconductor Devices, 2007
Electrical characteristics of hafnium oxide (HfO2)/silicon dioxide (SiO2) gate dielectric stack d... more Electrical characteristics of hafnium oxide (HfO2)/silicon dioxide (SiO2) gate dielectric stack during both constant voltage stress (CVS) and constant current stress (CCS) have been experimentally investigated with varying thickness of the HfO2 layer. The generation kinetics of bulk, interface and border trapped charges have been discussed showing a correlation among them. Nature of intrinsic hole traps in SiO2 has also been studied from an independent charge relaxation experiment. In addition, time-dependent dielectric breakdown (TDDB) has been studied during CVS.
Physica Status Solidi (a), 1995
... 0.5 PIYAS SAMANTA and CK SARKAR I ... In order to quantitatively understand the trapping beha... more ... 0.5 PIYAS SAMANTA and CK SARKAR I ... In order to quantitatively understand the trapping behaviorde-pendence on the injection techniques, we have used the value of the initial constant, applied field E,, equal to the value of the cathode field E, during constant current stress. ...
Solid-State Electronics, 2002
A theoretical investigation on the gate polarity dependence of Fowler–Nordheim (FN) tunneling ele... more A theoretical investigation on the gate polarity dependence of Fowler–Nordheim (FN) tunneling electron initiated impact ionization probabilities in the bulk silicon dioxide (SiO2) films as well as hole injection from the anode material (n+ poly-Si gate or silicon substrate) in metal-oxide-silicon devices is presented. Our theoretical results of the gate polarity dependence of the probabilities of various impact ionization processes
Semiconductor Science and Technology, 2006
A comprehensive analysis of the stress-induced leakage current (SILC) through thermally grown ult... more A comprehensive analysis of the stress-induced leakage current (SILC) through thermally grown ultrathin silicon dioxide (SiO2) films has been presented based on experimental observations. Stressing and sensing measurements are done in tantalum nitride (TaN) gate metal-oxide-silicon (MOS) capacitors at negative gate bias in the direct tunnelling (DT) regime. Both transient and steady-state DT SILCs have been studied in oxides with
Semiconductor Science and Technology, 1996
... current stress Piyas Samanta† and CK Sarkar‡ † Department of Physics, Jadavpur University, Ca... more ... current stress Piyas Samanta† and CK Sarkar‡ † Department of Physics, Jadavpur University, Calcutta 32, India ‡ Department of Electronics & Telecommunication Engineering, Jadavpur University, Calcutta 32, India ... σr〉 = ∫ Ea Ec σr(E)dE /∫ Ea ...
Microelectronics Reliability, 2010
We compare charge carrier generation/trapping related degradation in control oxide (SiO 2) and Hf... more We compare charge carrier generation/trapping related degradation in control oxide (SiO 2) and HfO 2 /SiO 2 stack of an identical equivalent-oxide-thickness (EOT) during constant gate voltage stress of n-type metal-oxide-semiconductor (nMOS) capacitors. Irrespective of these two dielectrics, the kinetics of generation of both surface states and oxide-trapped positive charges are found to be similar. Our analysis shows that the positive oxide charge buildup during CVS is due to trapping of protons by the strained SiAOASi bonds in either of the devices. We demonstrate that compared to SiO 2 devices, HfO 2 devices with an equal EOT better perform in CMOS logic applications. On the other hand, our results indicate that the control oxide is better in charge trapping memory devices. Furthermore, the lifetime of the control oxide devices is observed longer than that of HfO 2 devices at a given operating voltage.
Microelectronic Engineering, 2007
We have investigated electrical stress-induced charge carrier generation/trapping in a 4.2 nm thi... more We have investigated electrical stress-induced charge carrier generation/trapping in a 4.2 nm thick (physical thickness T phy) hafnium oxide (HfO 2)/silicon dioxide (SiO 2) dielectric stack in metal-oxide-semiconductor (MOS) capacitor structures with negative bias on the gate. It is found that electron trapping is suppressed in our devices having an equivalent oxide thickness (EOT) as low as 2.4 nm. Our measurement results indicate that proton-induced defect generation is the dominant mechanism of generation of bulk, border and interface traps during stress. In addition, we have shown that constant voltage stress (CVS) degrades the dielectric quality more than constant current stress (CCS).
Journal of The Electrochemical Society, 2009
[Journal of The Electrochemical Society 156, H661 (2009)]. Piyas Samanta, Chin-Lung Cheng, Yao-Je... more [Journal of The Electrochemical Society 156, H661 (2009)]. Piyas Samanta, Chin-Lung Cheng, Yao-Jen Lee. Abstract. ... Acknowledgment. PS thanks Dr. Souvik Mahapatra at Microelectronics Division, IIT, Bombay, for providing the measurement facilities. ...