Paulius Sakalas - Academia.edu (original) (raw)

Papers by Paulius Sakalas

Microelectronics Reliability, 2004

In this paper we present experimental results of dynamic thermal mapping for the characterization... more In this paper we present experimental results of dynamic thermal mapping for the characterization of electro-thermal behaviour of new power MOSFET devices during Unclamped Inductive Switching. Based on a suitable electrical driving circuit and on a direct radiometric detection of the device temperature, the proposed system is able to acquire the temperature map over the dye area with high spatial (less than 10μm) and time (less than 2μs) resolution, and good temperature (less than 1°C) resolution. This capabilities are confirmed by the results reported in the paper, where two different low voltage (less than 60V) low on-resistance (less than 10mΩ) multi-cellular power MOSFETs devices have been tested. Uneven temperature distributions due to differences in dye size and dissipated power have been detected during the UIS transient.

2020 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2020

This paper presents an ultra-wideband, 4 – 42.5 GHz Low Noise Amplifier (LNA), that stands out fo... more This paper presents an ultra-wideband, 4 – 42.5 GHz Low Noise Amplifier (LNA), that stands out for its flat small signal power gain (SSG) response, low DC power consumption and good linearity. Design approach for simultaneous noise and power matching was introduced. Based on this approach, combined transmission line and lumped element matching networks were implemented. Without employing a negative feedback, a 1.5 dB gain flatness and a good noise matching was achieved over an ultra-wide bandwidth. Designed in a commercial 0.25 µm GaAs pHEMT process, the 2-stage LNA exhibits an SSG of 13 dB, a minimum noise figure of 3.6 dB, OIP2 and OIP3 greater than 38 dBm and 25 dBm respectively. The total die area is 2.4 mm2, whereas the circuit consumes 32.5 mA from a 4 V DC power source.

2006 68th ARFTG Conference: Microwave Measurement, 2006

A novel automated wafer-level RF measurement system is presented. It includes a wafer prober and ... more A novel automated wafer-level RF measurement system is presented. It includes a wafer prober and dedicated on-wafer probe tips and calibration standards. Probe station related design issues are discussed leading to a system for automated testing of wafers up to 300mm by using a programmable positioning stage. Using on-wafer SiGe HBT measurements, noise characterization and VNA calibration verification, the long-term stability and reliability of the setup is illustrated. Tests are carried out both with liquid nitrogen as well as liquid helium as coolant, equal to temperature range from 400K down to 4K.

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2021

2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2019

This paper presents an ultra-wideband 8-45 GHz FMCW MIMO radar transmitter (Tx) front-end, design... more This paper presents an ultra-wideband 8-45 GHz FMCW MIMO radar transmitter (Tx) front-end, designed in a 130 nm SiGe BiCMOS technology. Various design techniques were applied to achieve the ultra-wide bandwidth, high linearity and the output power, which is at the edge for the given technology. The measured output power at 1 dB compression point was 15 – 20 dBm in a frequency range of 8 – 45 GHz and 3 dB output power flatness of 17-20 dBm was achieved for a 9 – 41 GHz bandwidth. The compact design features a total active IC area of 2.72 mm2 and a peak overall system PAE of 9 %. The total DC power consumption was 1.45 W.

2021 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS), 2021

This work shows the design and measurements of a 28 GHz low-noise amplifier, realized in Globalfo... more This work shows the design and measurements of a 28 GHz low-noise amplifier, realized in Globalfoundries 45nm RFSOI CMOS technology. The enhanced linearity concept is based on the modified derivative superposition method. The presented measurements confirm a high IIP3 of 10 dBm, a power gain of 9 dB, a noise figure of 3.1 dB, and a total power consumption 34 mW from a 1.8 V supply voltage. The amplifier topology is built around an inductively degenerated, differential cascode amplifier with baluns and GSG pads at the input and output ports. In this paper, we extend our previous research results by providing deeper design insight, as well as experimental verification and comparison of the measurement results with the simulations.

2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), 2017

High frequency (h.f.) harmonic distortion (HD) of advanced InP heterojunction bipolar transistors... more High frequency (h.f.) harmonic distortion (HD) of advanced InP heterojunction bipolar transistors (HBTs) with various emitter widths was investigated. Geometry scalable parameters for the compact model (CM) HICUM/L2 v. 2.34, featuring a two-region base-collector capacitance formulation, were extracted from temperature dependent DC and AC measurements of HBTs and from the special test structures. Single tone harmonic distortion and active two tone load pull measurements were carried out for different emitter area devices. The compact model was used for data analysis.

IEEE Transactions on Microwave Theory and Techniques, 2021

2000 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium Digest of Papers (Cat. No.00CH37096)

Semiconductor Science and Technology, 2014

2015 IEEE Bipolar/BiCMOS Circuits and Technology Meeting - BCTM, 2015

An overview on the compact modeling activities within the DOTSEVEN project is given. Issues such ... more An overview on the compact modeling activities within the DOTSEVEN project is given. Issues such as geometry scaling, substrate coupling and thermal effects as well as HICUM Level 2 features enabling the accurate modeling of the linear and non-linear characteristics of the latest generation of SiGe HBTs are discussed. Furthermore, experimental results for the most important DC and small-signal characteristics as well as selected examples for non-linear modeling of the most advanced SiGe HBTs from two different technologies are presented. Model verification issues related to limited on-wafer high-frequency measurement capability and the accurate calibration at multi-hundred GHz are briefly touched.

2015 10th European Microwave Integrated Circuits Conference (EuMIC), 2015

A two stage cascode low noise amplifier using tapered inductors with optimized quality factors wa... more A two stage cascode low noise amplifier using tapered inductors with optimized quality factors was designed in a 130 nm logic CMOS process. The K-band (24 GHz-26.5 GHz) LNA consumes 11.25 mW DC power for a supply voltage of 1.5 V, achieves 27.5 dB peak transducer gain and 3.88 dB noise figure (NF) at 25 GHz. S11 and S22 at 25 GHz are -13 dB and -10 dB, respectively. It achieves a minimum NF of 3.5 dB at 24 GHz and within the entire frequency band of interest the NF is less than 5 dB. IIP3 of the LNA is -11 dBm and the LNA including pads occupies an area of 830μm × 800μm.

… WSL (IMS/RFIC)- …, 2009

Please be patient while the object screen loads. Changez de vue : Choisir un site… UCL FUNDP FUSL... more Please be patient while the object screen loads. Changez de vue : Choisir un site… UCL FUNDP FUSL FUCaM. ...

IEEE Transactions on Electron Devices, 1982

2016 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), 2016

A two stage ultra-wideband low noise amplifier (LNA) MMIC was designed and fabricated based on ac... more A two stage ultra-wideband low noise amplifier (LNA) MMIC was designed and fabricated based on active impedance matching technique and SiGe BiCMOS technology. The measured performance featuring transducer gain of 10.2 dB, noise figure below 4.7 dB, -3 dB bandwidth of 50 GHz and 8.06 mW DC power consumption, yields by far the best figure of merit (FOM) reported up to date. The proposed LNA exhibits a great degree of design simplicity and requires a total chip area of only 0.16 mm2.

Abstract-A time-dependent effective-mass Schrödinger-Poisson solver is used to study the frequenc... more Abstract-A time-dependent effective-mass Schrödinger-Poisson solver is used to study the frequency dependence of the gate capacitance of a short Schottky-barrier carbon nanotube field-effect transistor (CNTFET). A delayed (re)charging of the channel causes a (non-quasi-static) drop of the gate capacitance for higher frequencies on a characteristic scale, which can be related to the escape time of the carriers. The impact of Schottky-barriers on the escape time is discussed both analytically and by means of transient simulations. A comparison with experimental data reveals an interesting qualitative similarity. Index Terms-CNTFET, ballistic transport, high-frequency behavior, gate capacitance, double barrier structure, non-quasistatic phenomena, escape time

HF noise parameters were measured and modeled for the first time for wafer-scale manufacturable C... more HF noise parameters were measured and modeled for the first time for wafer-scale manufacturable CNTFETs. These first multi-tube multi-fin ger CNTFETs exhibit still rela­ tively high values for the minimum noise figure (NF min = 3.5 dB at 1 GHz). Based on detailed compact modelin g, the ori gin of this noise can be explained by the existence of the parasitic network and metallic tubes. Keywords-compone nt:

IEEE Transactions on Microwave Theory and Techniques, 2021

A 190-GHz mixer-based down-conversion receiver realized in a 130-nm SiGe BiCMOS technology featur... more A 190-GHz mixer-based down-conversion receiver realized in a 130-nm SiGe BiCMOS technology featuring high-speed heterojunction bipolar transistors (HBTs) with (<inline-formula> <tex-math notation="LaTeX">$f_{\text {T}}$ </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">$f_{\text {max}}$ </tex-math></inline-formula>) = (300, 500) GHz is presented. The core part of the receiver consists of a low-noise amplifier (LNA), an active tunable fundamental mixer, an intermediate frequency (IF) buffer amplifier (BA), and an active inverse balun. A wideband, high conversion gain (CG) local oscillator (LO) chain is integrated to make the receiver suitable for applications requiring tunable LO, which contains a multiplier with a multiplication factor of 12 (<inline-formula> <tex-math notation="LaTeX">$\times 12$ </tex-math></inline-formula>) and a driver amplifier. To exploit the best possible performance with ultralow dc power consumption (<inline-formula> <tex-math notation="LaTeX">$P_{\text {dc}}$ </tex-math></inline-formula>), the mixer and LNA transistors operate at forward-biased base–collector junction voltage (<inline-formula> <tex-math notation="LaTeX">$V_{\text {BC}}$ </tex-math></inline-formula>). With a fixed IF frequency at 1 GHz, this receiver exhibits a peak CG of 49 dB with a 14-dB tuning range and a minimum single-sideband noise figure (NF) of 16.5 dB, consuming only 29-mW static dc power for the core part and 171 mW overall, including the LO chain. Within the CG tuning range, this receiver achieves a 6-dB RF bandwidth (BW) from 25 to 32 GHz. Compared with previously reported receivers at similar frequencies, the highest CG and the lowest <inline-formula> <tex-math notation="LaTeX">$P_{\text {dc}}$ </tex-math></inline-formula> with highly competitive performance in terms of BW, CG tuning range, 1-dB output compression point, and NF have been achieved.

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2021

Microelectronics Reliability, 2004

In this paper we present experimental results of dynamic thermal mapping for the characterization... more In this paper we present experimental results of dynamic thermal mapping for the characterization of electro-thermal behaviour of new power MOSFET devices during Unclamped Inductive Switching. Based on a suitable electrical driving circuit and on a direct radiometric detection of the device temperature, the proposed system is able to acquire the temperature map over the dye area with high spatial (less than 10μm) and time (less than 2μs) resolution, and good temperature (less than 1°C) resolution. This capabilities are confirmed by the results reported in the paper, where two different low voltage (less than 60V) low on-resistance (less than 10mΩ) multi-cellular power MOSFETs devices have been tested. Uneven temperature distributions due to differences in dye size and dissipated power have been detected during the UIS transient.

2020 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2020

This paper presents an ultra-wideband, 4 – 42.5 GHz Low Noise Amplifier (LNA), that stands out fo... more This paper presents an ultra-wideband, 4 – 42.5 GHz Low Noise Amplifier (LNA), that stands out for its flat small signal power gain (SSG) response, low DC power consumption and good linearity. Design approach for simultaneous noise and power matching was introduced. Based on this approach, combined transmission line and lumped element matching networks were implemented. Without employing a negative feedback, a 1.5 dB gain flatness and a good noise matching was achieved over an ultra-wide bandwidth. Designed in a commercial 0.25 µm GaAs pHEMT process, the 2-stage LNA exhibits an SSG of 13 dB, a minimum noise figure of 3.6 dB, OIP2 and OIP3 greater than 38 dBm and 25 dBm respectively. The total die area is 2.4 mm2, whereas the circuit consumes 32.5 mA from a 4 V DC power source.

2006 68th ARFTG Conference: Microwave Measurement, 2006

A novel automated wafer-level RF measurement system is presented. It includes a wafer prober and ... more A novel automated wafer-level RF measurement system is presented. It includes a wafer prober and dedicated on-wafer probe tips and calibration standards. Probe station related design issues are discussed leading to a system for automated testing of wafers up to 300mm by using a programmable positioning stage. Using on-wafer SiGe HBT measurements, noise characterization and VNA calibration verification, the long-term stability and reliability of the setup is illustrated. Tests are carried out both with liquid nitrogen as well as liquid helium as coolant, equal to temperature range from 400K down to 4K.

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2021

2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2019

This paper presents an ultra-wideband 8-45 GHz FMCW MIMO radar transmitter (Tx) front-end, design... more This paper presents an ultra-wideband 8-45 GHz FMCW MIMO radar transmitter (Tx) front-end, designed in a 130 nm SiGe BiCMOS technology. Various design techniques were applied to achieve the ultra-wide bandwidth, high linearity and the output power, which is at the edge for the given technology. The measured output power at 1 dB compression point was 15 – 20 dBm in a frequency range of 8 – 45 GHz and 3 dB output power flatness of 17-20 dBm was achieved for a 9 – 41 GHz bandwidth. The compact design features a total active IC area of 2.72 mm2 and a peak overall system PAE of 9 %. The total DC power consumption was 1.45 W.

2021 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS), 2021

This work shows the design and measurements of a 28 GHz low-noise amplifier, realized in Globalfo... more This work shows the design and measurements of a 28 GHz low-noise amplifier, realized in Globalfoundries 45nm RFSOI CMOS technology. The enhanced linearity concept is based on the modified derivative superposition method. The presented measurements confirm a high IIP3 of 10 dBm, a power gain of 9 dB, a noise figure of 3.1 dB, and a total power consumption 34 mW from a 1.8 V supply voltage. The amplifier topology is built around an inductively degenerated, differential cascode amplifier with baluns and GSG pads at the input and output ports. In this paper, we extend our previous research results by providing deeper design insight, as well as experimental verification and comparison of the measurement results with the simulations.

2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), 2017

High frequency (h.f.) harmonic distortion (HD) of advanced InP heterojunction bipolar transistors... more High frequency (h.f.) harmonic distortion (HD) of advanced InP heterojunction bipolar transistors (HBTs) with various emitter widths was investigated. Geometry scalable parameters for the compact model (CM) HICUM/L2 v. 2.34, featuring a two-region base-collector capacitance formulation, were extracted from temperature dependent DC and AC measurements of HBTs and from the special test structures. Single tone harmonic distortion and active two tone load pull measurements were carried out for different emitter area devices. The compact model was used for data analysis.

IEEE Transactions on Microwave Theory and Techniques, 2021

2000 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium Digest of Papers (Cat. No.00CH37096)

Semiconductor Science and Technology, 2014

2015 IEEE Bipolar/BiCMOS Circuits and Technology Meeting - BCTM, 2015

An overview on the compact modeling activities within the DOTSEVEN project is given. Issues such ... more An overview on the compact modeling activities within the DOTSEVEN project is given. Issues such as geometry scaling, substrate coupling and thermal effects as well as HICUM Level 2 features enabling the accurate modeling of the linear and non-linear characteristics of the latest generation of SiGe HBTs are discussed. Furthermore, experimental results for the most important DC and small-signal characteristics as well as selected examples for non-linear modeling of the most advanced SiGe HBTs from two different technologies are presented. Model verification issues related to limited on-wafer high-frequency measurement capability and the accurate calibration at multi-hundred GHz are briefly touched.

2015 10th European Microwave Integrated Circuits Conference (EuMIC), 2015

A two stage cascode low noise amplifier using tapered inductors with optimized quality factors wa... more A two stage cascode low noise amplifier using tapered inductors with optimized quality factors was designed in a 130 nm logic CMOS process. The K-band (24 GHz-26.5 GHz) LNA consumes 11.25 mW DC power for a supply voltage of 1.5 V, achieves 27.5 dB peak transducer gain and 3.88 dB noise figure (NF) at 25 GHz. S11 and S22 at 25 GHz are -13 dB and -10 dB, respectively. It achieves a minimum NF of 3.5 dB at 24 GHz and within the entire frequency band of interest the NF is less than 5 dB. IIP3 of the LNA is -11 dBm and the LNA including pads occupies an area of 830μm × 800μm.

… WSL (IMS/RFIC)- …, 2009

Please be patient while the object screen loads. Changez de vue : Choisir un site… UCL FUNDP FUSL... more Please be patient while the object screen loads. Changez de vue : Choisir un site… UCL FUNDP FUSL FUCaM. ...

IEEE Transactions on Electron Devices, 1982

2016 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), 2016

A two stage ultra-wideband low noise amplifier (LNA) MMIC was designed and fabricated based on ac... more A two stage ultra-wideband low noise amplifier (LNA) MMIC was designed and fabricated based on active impedance matching technique and SiGe BiCMOS technology. The measured performance featuring transducer gain of 10.2 dB, noise figure below 4.7 dB, -3 dB bandwidth of 50 GHz and 8.06 mW DC power consumption, yields by far the best figure of merit (FOM) reported up to date. The proposed LNA exhibits a great degree of design simplicity and requires a total chip area of only 0.16 mm2.

Abstract-A time-dependent effective-mass Schrödinger-Poisson solver is used to study the frequenc... more Abstract-A time-dependent effective-mass Schrödinger-Poisson solver is used to study the frequency dependence of the gate capacitance of a short Schottky-barrier carbon nanotube field-effect transistor (CNTFET). A delayed (re)charging of the channel causes a (non-quasi-static) drop of the gate capacitance for higher frequencies on a characteristic scale, which can be related to the escape time of the carriers. The impact of Schottky-barriers on the escape time is discussed both analytically and by means of transient simulations. A comparison with experimental data reveals an interesting qualitative similarity. Index Terms-CNTFET, ballistic transport, high-frequency behavior, gate capacitance, double barrier structure, non-quasistatic phenomena, escape time

HF noise parameters were measured and modeled for the first time for wafer-scale manufacturable C... more HF noise parameters were measured and modeled for the first time for wafer-scale manufacturable CNTFETs. These first multi-tube multi-fin ger CNTFETs exhibit still rela­ tively high values for the minimum noise figure (NF min = 3.5 dB at 1 GHz). Based on detailed compact modelin g, the ori gin of this noise can be explained by the existence of the parasitic network and metallic tubes. Keywords-compone nt:

IEEE Transactions on Microwave Theory and Techniques, 2021

A 190-GHz mixer-based down-conversion receiver realized in a 130-nm SiGe BiCMOS technology featur... more A 190-GHz mixer-based down-conversion receiver realized in a 130-nm SiGe BiCMOS technology featuring high-speed heterojunction bipolar transistors (HBTs) with (<inline-formula> <tex-math notation="LaTeX">$f_{\text {T}}$ </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">$f_{\text {max}}$ </tex-math></inline-formula>) = (300, 500) GHz is presented. The core part of the receiver consists of a low-noise amplifier (LNA), an active tunable fundamental mixer, an intermediate frequency (IF) buffer amplifier (BA), and an active inverse balun. A wideband, high conversion gain (CG) local oscillator (LO) chain is integrated to make the receiver suitable for applications requiring tunable LO, which contains a multiplier with a multiplication factor of 12 (<inline-formula> <tex-math notation="LaTeX">$\times 12$ </tex-math></inline-formula>) and a driver amplifier. To exploit the best possible performance with ultralow dc power consumption (<inline-formula> <tex-math notation="LaTeX">$P_{\text {dc}}$ </tex-math></inline-formula>), the mixer and LNA transistors operate at forward-biased base–collector junction voltage (<inline-formula> <tex-math notation="LaTeX">$V_{\text {BC}}$ </tex-math></inline-formula>). With a fixed IF frequency at 1 GHz, this receiver exhibits a peak CG of 49 dB with a 14-dB tuning range and a minimum single-sideband noise figure (NF) of 16.5 dB, consuming only 29-mW static dc power for the core part and 171 mW overall, including the LO chain. Within the CG tuning range, this receiver achieves a 6-dB RF bandwidth (BW) from 25 to 32 GHz. Compared with previously reported receivers at similar frequencies, the highest CG and the lowest <inline-formula> <tex-math notation="LaTeX">$P_{\text {dc}}$ </tex-math></inline-formula> with highly competitive performance in terms of BW, CG tuning range, 1-dB output compression point, and NF have been achieved.

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2021