Marek Perkowski - Profile on Academia.edu (original) (raw)

Papers by Marek Perkowski

European Design Automation Conference, Nov 1, 1992

The paper presents a new approach to the decomposition of incompletely specified Boolean function... more The paper presents a new approach to the decomposition of incompletely specified Boolean functions and its application to LUT-based FPGA mapping. Three methods were developed: the fast Graph Coloring to pe?form a quasi-optimum don' t care assignment, the Variable Partitioning to quicklyjind the "best" partitions, and the Local Transformation to tran~orm a nondecomposable function into several decomposable ones. The presented methods perform global optindzation of the input function, while most of the other existing methods recursively perform only local optimization on some kinds of network-like graphs and few of them can handle incompletely specijied functions. A short description of a FPGA mapping program (TUDE) and an evaluation of its results are also provided.

Quantum Information & Computation, May 1, 2020

Designing a quantum oracle is an important step in practical realization of Grover algorithm, the... more Designing a quantum oracle is an important step in practical realization of Grover algorithm, therefore it is useful to create methodologies to design oracles. Lattice diagrams are regular two-dimensional structures that can be directly mapped onto a quantum circuit. We present a quantum oracle design methodology based on lattices. The oracles are designed with a proposed method using generalized Boolean symmetric functions realized with lattice diagrams. We also present a decomposition-based algorithm that transforms non-symmetric functions into symmetric or partially symmetric functions. Our method, which combines logic minimization, logic decomposition, and mapping, has lower quantum cost with fewer ancilla qubits. Overall, we obtain encouraging synthesis results superior to previously published data.

Symbolic algebraic computer programs. Part II. Applications and perspectives

Postepy Astronomii Krakow, Mar 1, 1978

Springer eBooks, 1998

The design of a high-frequency ®eld-programmable analog array (FPAA) is presented. The FPAA is ba... more The design of a high-frequency ®eld-programmable analog array (FPAA) is presented. The FPAA is based on a regular pattern of cells interconnected locally for high frequency performance. No switches of any kind are used in the signal path of a cell: programming of the functions, parameters, and interconnections is achieved solely by modifying cells' bias conditions digitally. Limited global signal interconnections are also available for those application circuits which cannot be mapped onto locally-only interconnected structure. Key circuits of the FPAA have been fabricated in a CPI transistor-array bipolar technology.

Inverse problems, constraint satisfaction, reversible logic, invertible logic and Grover quantum oracles for practical problems

Science of Computer Programming, Jun 1, 2022

Field Programmable Gate Arrays, Aug 31, 1992

The new family of Field Programmable Gate Arrays, CLI6000 from Concurrent Logic Inc realizes the ... more The new family of Field Programmable Gate Arrays, CLI6000 from Concurrent Logic Inc realizes the truly Cellular Logic. It has been mainly designed for the realization of data path architectures. However, introduced by it new universal logic cell calls also for new logic synthesis methods based o n r egularity of connections. In this paper we present two programs, exact and approximate, for the minimization of Permuted R eed-Muller Trees that are obtained b y r epetitive application of Davio expansions (Shannon expansions for EXOR gates) in all possible orders of variables in subtrees. Such trees are p articularly well matched t o b oth the realization of logic cell and connection structure of the CLI6000 device. It is shown on several standard b enchmarks that the heuristic algorithm gives good quality results in much less time than the exact algorithm.

Synthesis of memristive circuits based on stateful IMPLY gates using an evolutionary algorithm with a correction function

International Symposium on Nanoscale Architectures, Jul 18, 2016

Synthesis of stateful memristor-based logic circuits is realized with a multi-stage evolutionary ... more Synthesis of stateful memristor-based logic circuits is realized with a multi-stage evolutionary algorithm (IMP_MSEA) which minimizes the total circuit delay. This is done by minimizing the number of pulses to control the circuit. We assume different numbers of working memristors in the circuit and compare the delay results for each. The error of the synthesized circuit is the number of min-terms that differ between the truth table of the function of the resultant circuit and the truth table that specifies this circuit. We formulate a circuit minimization problem in which error should be zero or should be restricted to a small value. The system uses the concept of correction functions when the error is very low and a new round of evolution starts for the correcting function. The logic circuit design includes coding and initialization methods to reduce illegal and redundant solutions of random initial population. Experiments with 2 to 11 input single-output functions demonstrate that the algorithm can deal with various assumed numbers of working memristors and for many benchmark functions it significantly reduces the delay.

New Families of Reversible Expansions and Their Regular Lattice Circuits

Soft Computing, 2005

ABSTRACT

IEEE Micro, May 1, 2002

This article proposes using symbolic learning methods based on multiple-valued (MV) logic and imp... more This article proposes using symbolic learning methods based on multiple-valued (MV) logic and implemented in reconfigurable hardware. In the part one, we discussed why symbolic learning is useful in some applications, such as robotics. We presented an architecture for a massively parallel reconfigurable processor that enables speeding up logic operations performed in learning hardware. Rather than learning using evolutionary and neural network methods in hardware, our approach uses combinatorial synthesis methods developed in the framework of the logic synthesis approach in digital-circuitdesign automation. In contrast to previous approaches to evolvable hardware that so far have dominated the learning in reconfigurable systems, here the learning takes place on the level of constraint acquisition and quasioptimal logic synthesis rather than on the lower level of programming binary switches based on (close to random) decisions of evolutionary programming methods. Our learning strategy is based on the principle of Occam's Razor, which facilitates generalization, discovery, and strong learning methods. We realize directly in reconfigurable hardware such MV cube-algebra operators as intersection, supercube, sharp, and crosslink, and such algorithms as disjunctive normal form (DNF) minimization, Ashenhurst/Curtis decomposition, satisfiability, and decision tree generation. Part two of our article presents cube calculus in more detail as well as various aspects of realizing cube calculus operations in hardware. We also evaluate two variants of our experimental designs. Let's consider discrete variables (attributes) X 1 , X 2 , ... , X n , such that each variable X i can take values from a certain finite discrete set V i (V i can be any finite set of symbols). A literal X i

Logic synthesis and a generalized notation for memristor-realized material implication gates

International Conference on Computer Aided Design, Nov 3, 2014

The paper presents new logic synthesis methods for single-output incomplete multi-level binary ci... more The paper presents new logic synthesis methods for single-output incomplete multi-level binary circuits using Memristor-based material implication gates. The first method follows Lehtonen's assumption of using only two working memristors. The algorithm minimizes the number of implication (IMPLY) gates, which corresponds to minimizing the number of pulses or the delay time. This greedy search method uses essential and secondary essential primes, does not require solving the covering problem, is fast, and produces high quality results. We compare it to other synthesis methods, such as the modified SOP and Exclusive-Or Sum of Products (ESOP) with minimum number of working memristors. We analyze the problem of reduction in IMPLY gate count by adding more working memristors and introduce Imply Sequence Diagrams, a new notation, similar to one used in reversible logic.

DIADES-a high level synthesis system

Abstract The DIADES design automation system is presented. DIADES performs system-and high-level ... more Abstract The DIADES design automation system is presented. DIADES performs system-and high-level synthesis of digital systems, as well as logic synthesis. It synthesizes a structural hardware description. The need for advances in synthesis and some basic design ...

Detecting Affine Equivalence Of Boolean Functions And Circuit Transformation

The Computer Journal, Jul 1, 2022

Affine equivalence of Boolean functions has various applications in computer science and modern c... more Affine equivalence of Boolean functions has various applications in computer science and modern cryptography, such as circuit design and S-boxes. Existing methods for detecting affine equivalence of Boolean functions work in some cases but not when the truth table of a Boolean function is sparse. To improve previous methods and overcome this limitation, we propose a method by transforming the Boolean function to a function with the property that its function values at the orthonormal basis are all equal to 1 or 0, which narrows down the search space of affine transformations. Our first algorithm has the advantage of getting a smaller search space than previous methods and is especially useful for sparse functions. Specifically, when the Boolean functions are sparse, the search space can be reduced exponentially in average and experiments show the efficiency of our first algorithm. We then present another algorithm to transform one circuit into its equivalent affine circuit by synthesizing a reversible circuit and inserting it in front of the original circuit. To our knowledge, this is the first work to automatically synthesize an affine equivalent circuit for any given circuit and the first to do this by combining reversible circuit and non-reversible circuit.

Session details: Methods and representations for logic synthesis

Symbolic algebraic computer programs. Part I. The LISP programming language

Postepy Astronomii Krakow, 1977

The truth-table defining  may raise some doubts, especially when we "compare" it with the intuit... more The truth-table defining  may raise some doubts, especially when we "compare" it with the intuitive notion of implication. 2. In order to clarify the issue, Lewis introduced the notion of strict implication, and with it the symbol of a new logical connective:  Modal Logic: Possible and necessary Modal Equivalence:       -Sentence " it is possible that it will rain in afternoon" is equivalent to the sentence "it is not necessary that it will not rain in afternoon" -Sentence " it is possible that this Boolean function is satisfied" is equivalent to the sentence "it is not necessary that this Boolean function is not satisfied".

A General Data Mining Methodology Based on a Weighted Hierarchical Adaptive Voting Ensemble (WHAVE) Machine Learning Method

J. Multiple Valued Log. Soft Comput., 2017

Minimization of Ternary Reversible Logic Cascades Using a Universal Subset of Generalized Ternary Gates

Soft Computing, 2007

Quantum Algorithm for Maximum Satisfiability

Proof of Activity Consensus Algorithm Based on Credit Reward Mechanism

Lecture Notes in Computer Science, 2020

A fast computer implementation of adding and arithmetic multi-polarity transforms for logic design

A novel computer algorithm that generates adding and arithmetic multipolarity transforms of compl... more A novel computer algorithm that generates adding and arithmetic multipolarity transforms of completely and incompletely specified Boolean functions is discussed. The algorithm generates the spectra directly from the minterm representation of a function without performing a matrix multiplication. When used for Boolean function transformations, these transforms are one-to-one mappings in a binary/ternary vector space.<<ETX>>