Phil Oldiges - Academia.edu (original) (raw)

Papers by Phil Oldiges

Novel device structures with vertical channels gated by TSV's are demonstrated. The unique de... more Novel device structures with vertical channels gated by TSV's are demonstrated. The unique device structure is realized in a standard TSV process flow, without new material systems or processes. They can be used for both characterizing the TSV process as well as enable new functions. They can be easily integrated into product designs thus enabling field monitoring.

A stacked transistor on SOI shows the potential to provide soft error upset immune designs. Key d... more A stacked transistor on SOI shows the potential to provide soft error upset immune designs. Key design elements are presented and analyzed showing tradeoffs between standard SOI devices and stacked devices, as well as alternative layouts to optimize soft error upset immunity.

Symposium on VLSI Technology, Jun 14, 2011

FinFET devices achieving N/P Ion values of 1250/950 uA/um at 100nA/um at 1V, 1300/1000 uA/um with... more FinFET devices achieving N/P Ion values of 1250/950 uA/um at 100nA/um at 1V, 1300/1000 uA/um with self-heating correction, are demonstrated, using a dual work function gate-first process flow at 100 nm gate pitch and 40 nm fin pitch. Ring-oscillator (RO, FO=3) functionality has been demonstrated, showing excellent Vdd scalability. We have also demonstrated logic scan chain functionality and yield improvement

2016 IEEE International Electron Devices Meeting (IEDM), 2016

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metalliza... more We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.

2008 IEEE International SOI Conference, 2008

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014

We report a novel approach to enable the fabrication of dielectric isolated FinFETs on bulk subst... more We report a novel approach to enable the fabrication of dielectric isolated FinFETs on bulk substrates by bottom oxidation through STI (BOTS). BOTS FinFET transistors are manufactured with 42nm fin pitch and 80nm contacted gate pitch. Competitive device performances are achieved with effective drive currents of Ieff (N/P) = 621/453 μA/μm at Ioff = 10 nA/μm at VDD = 0.8 V. The BOTS process results in a sloped fin profile at the fin bottom (fin tail). By extending the gate vertically into the fin tail region, the parasitic short-channel effects due to this fin tail have been successfully suppressed. We further demonstrate the extension of the BOTS process to the fabrication of strained SiGe FinFETs and nanowires, providing a path for future CMOS technologies.

2017 Symposium on VLSI Technology, 2017

Journal of The Electrochemical Society, 1999

A new model for simulating the reverse short channel effect and capacitance-voltage (C-V) charact... more A new model for simulating the reverse short channel effect and capacitance-voltage (C-V) characteristics of metal-oxide-semiconductor (MOS) transistors has been developed. Due to ion-implantation and stress effects, the interface between Si and SiO 2 in the model described here has been assumed to be a nonuniform sink of interstitials. The simulator ALAMODE and the two-dimensional (2D) process simulator TSUPREM4 were used to simulate doping profiles of n-channel MOS (NMOS) devices. Using simulated 2D doping profiles, the threshold voltage and C-V curves of NMOS devices were calculated. We show comparisons of the threshold voltage, C-V curves, and channel doping profiles for extracted profiles using inverse modeling techniques and those simulated by ALAMODE and TSUPREM4. Using default model parameters in TSUPREM4, the doping profiles did not match extracted doping profiles well, but with the model described here incorporated into TSUPREM4 using calibrated model parameters, a good match between measurements and simulations was observed. The body effect and C-V characteristics of NMOS devices are quantitatively predicted using parameters obtained from matching of experimental threshold voltage data. We describe the model and implementation and discuss the physical significance of the new model.

Journal of Applied Physics, 2012

IEEE Transactions on Nuclear Science

SISPAD '97. 1997 International Conference on Simulation of Semiconductor Processes and Devices. Technical Digest

2019 IEEE Albany Nanotechnology Symposium (ANS), 2019

The bottom electrode (heater) in a mushroom cell phase change memory (PCM) is one of the major co... more The bottom electrode (heater) in a mushroom cell phase change memory (PCM) is one of the major components which determines device performance. Understanding the effect of heater geometry on Reset characteristics is necessary for engineering and fabricating efficient structures. In this paper, we explore the role of certain geometrical parameters of the heater using computer simulations. Performing such parameter sweeps experimentally would be uneconomical and time consuming. Our results indicate that the heater top radius/area is of utmost importance for Reset Current and cross-sectional area of the heater matters more that the actual shape of the cross-section. The focus of this paper is to provide a qualitative understanding of the variation of quantities of interest as the heater configuration is changed.

2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2018

A simple inline measurement technique for extracting the individual resistance components of the ... more A simple inline measurement technique for extracting the individual resistance components of the source, drain, and channel on a single MOSFET device using DC measurements is proposed. Modeling data is used to prove the efficacy of the technique. This method can be applied to symmetric or asymmetric devices.

Inthis work,two-dimensional numerical device simulations and6-stage inverter chaindelaycalculatio... more Inthis work,two-dimensional numerical device simulations and6-stage inverter chaindelaycalculations aredonetoexamine whetheraggressive channel length scaling continually provides transistor performance gain andwhether metalgates (MG)offer potential fordevice scaling overpolygate(PG)forhighperformance (HP) applications. Oursimulation showthatforHP application (1)thereisan optimized channellength, atwhich maximumperformance gainisobtained bothforMG and PG;(2)Atshort channel length regime (<46nm), there is noperformance gainofQG-MG relative toPG duetolack ofcarrier confinement, whichresult inseveresub- threshold slope degradation ofQG-MG;(3)BE-MGstacks show10%gainonainverter delay overPG.

2011 Symposium on VLSI Technology - Digest of Technical Papers, 2011

The nature of FinFET devices prohibits continuous width scaling and introduces a digitization of ... more The nature of FinFET devices prohibits continuous width scaling and introduces a digitization of device width. As a consequence, devices are comprised of arrays of Fins ranging from one (SRAM) to a few tens of Fins. This introduces an intrinsic variation in the device that is absent in conventional planar devices. To build a reliable circuit, model parameters have to be provided that take account of the correct scaling behavior with increasing number of Fins for the composite device. For the first time we address in this paper how a composite Fin device can be modeled correctly. The statistical drive current and leakage current distribution are accurately modeled using the proposed methodology. We show that the DIBL vs. SS relationship for the composite device is an easily accessible indicator for the intrinsic variations observed in a composite device.

By applying appropriate tensor transformations for the subband solutions of electron and hole and... more By applying appropriate tensor transformations for the subband solutions of electron and hole and their transport properties, we demonstrated the capability of determining the phonon induced mobility for planar and FinFET MOSFET devices under arbitrary stress, wafer and channel orientations. The electron and hole mobilities for such devices are numerically solved and their angular dependences on wafer are shown. We further investigated the mobility trend under some high index gate orientation conditions that are of interest to current 14 nm FinFET technology