Piyush Kasat - Academia.edu (original) (raw)
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Papers by Piyush Kasat
Fourth International Conference on Advances in Recent Technologies in Communication and Computing (ARTCom2012), 2012
As Technology progresses, the speed of a digital system is of prime importance. Most complex syst... more As Technology progresses, the speed of a digital system is of prime importance. Most complex system use multipliers, and most often than not it is these multipliers which limit the speed of the system. Many high speed multipliers have been proposed in the past. Multipliers based on Vedic mathematics being one of them. Vedic multiplication algorithm is found to be fast as compared to other multiplication algorithms like Booth or Wallace. However the Vedic multiplier suffers from propagation delay for longer input lengths. A novel pipelined approach, consisting of seven stages is proposed here, so as to reduce the propagation delay. An 8*11 bit pipelined Vedic multiplier to be used for DCT applications is proposed and implemented. It is found to have a maximum clock speed of 179.69 MHz, and an area consisting of 225 slices.
2013 Tenth International Conference on Wireless and Optical Communications Networks (WOCN), 2013
ABSTRACT The Discrete Cosine Transform (DCT) is largely used for image and video compression in s... more ABSTRACT The Discrete Cosine Transform (DCT) is largely used for image and video compression in standards like JPEG and MPEG2. Its simplicity coupled with the fact that it can be computed faster than the Discrete Wavelet Transform (DWT) makes it an attractive option for image and video compression. Consequently a lot of research is in progress to determine novel architectures and algorithms for faster DCT computation having high throughput so that it can even be used for real time applications. For example, when transmitting and receiving videos, which have been compressed using MPEG2, one would like to receive the video, without any buffering delay. In other words, one requires such an architecture, which provides the DCTQ coeffecients at a consistent rate, with very low latency between two coeffecients. As such, a highly parallel and pipelined architecture employing 57 pipeline stages and using fast multipliers and adders is proposed in this work. The proposed DCT Processor is implemented in Spartan 3E FPGA.
In today's digital world, where portable computers have become as small as the size of palm limit... more In today's digital world, where portable computers have become as small as the size of palm limitation on processing speed has increased. Thus there's a need for modification in the traditional approach to overcome this limitation. An implementation using parallel and pipelined approach could work at higher speed while occupying limited number of slices. Paper deals with analyzing and reviewing different multiplication algorithms viz. Vedic, Chinese, Wallace, Booth, Karatsuba and Toom-Cook by performing 11*8 bit multiplication using parallel and pipelined approach.
Fourth International Conference on Advances in Recent Technologies in Communication and Computing (ARTCom2012), 2012
As Technology progresses, the speed of a digital system is of prime importance. Most complex syst... more As Technology progresses, the speed of a digital system is of prime importance. Most complex system use multipliers, and most often than not it is these multipliers which limit the speed of the system. Many high speed multipliers have been proposed in the past. Multipliers based on Vedic mathematics being one of them. Vedic multiplication algorithm is found to be fast as compared to other multiplication algorithms like Booth or Wallace. However the Vedic multiplier suffers from propagation delay for longer input lengths. A novel pipelined approach, consisting of seven stages is proposed here, so as to reduce the propagation delay. An 8*11 bit pipelined Vedic multiplier to be used for DCT applications is proposed and implemented. It is found to have a maximum clock speed of 179.69 MHz, and an area consisting of 225 slices.
2013 Tenth International Conference on Wireless and Optical Communications Networks (WOCN), 2013
ABSTRACT The Discrete Cosine Transform (DCT) is largely used for image and video compression in s... more ABSTRACT The Discrete Cosine Transform (DCT) is largely used for image and video compression in standards like JPEG and MPEG2. Its simplicity coupled with the fact that it can be computed faster than the Discrete Wavelet Transform (DWT) makes it an attractive option for image and video compression. Consequently a lot of research is in progress to determine novel architectures and algorithms for faster DCT computation having high throughput so that it can even be used for real time applications. For example, when transmitting and receiving videos, which have been compressed using MPEG2, one would like to receive the video, without any buffering delay. In other words, one requires such an architecture, which provides the DCTQ coeffecients at a consistent rate, with very low latency between two coeffecients. As such, a highly parallel and pipelined architecture employing 57 pipeline stages and using fast multipliers and adders is proposed in this work. The proposed DCT Processor is implemented in Spartan 3E FPGA.
In today's digital world, where portable computers have become as small as the size of palm limit... more In today's digital world, where portable computers have become as small as the size of palm limitation on processing speed has increased. Thus there's a need for modification in the traditional approach to overcome this limitation. An implementation using parallel and pipelined approach could work at higher speed while occupying limited number of slices. Paper deals with analyzing and reviewing different multiplication algorithms viz. Vedic, Chinese, Wallace, Booth, Karatsuba and Toom-Cook by performing 11*8 bit multiplication using parallel and pipelined approach.