Pochang Hsu - Academia.edu (original) (raw)

Papers by Pochang Hsu

Microelectronics Journal, 1994

,4 knowledge-based simulation environment is developed to facilitate the early design of Multichi... more ,4 knowledge-based simulation environment is developed to facilitate the early design of Multichip Modules (MCMs). Electrical system performance measures such as module clock frequency, etc. are predicted and analyzed for different interconnect and packaging technologies. Performance-limiting factors such as power dissipation, coupled noise, and simultaneous switching noise are also included in this work. CMOS based MCMs for workstation applications are used to demonstrate the feasibilitY of the system in development.

The packaging design support environment (PDSE) is a software system being developed at the Unive... more The packaging design support environment (PDSE) is a software system being developed at the University of Arizona to facilitate the analysis and design of packaging structures for microelectronic integrated circuits, a subject which is becoming one of increasing iruportance with higher circuit integration and system perfor1nanc.e. PDSE provides a platform for work in several active research areas including interconnect and packaging modeling and simulation in electrical, thermal, and thermal-mechanical aspects, ('AD framework development and evaluations for performance, riianufacturability, and reliability, etc. This paper describes the overall architecture and characteristics of the PDSE system in development, its implementation and applications.

IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 1993

The effects of interconnection loss (both dc loss and skin effect loss) on crosstalk noise for a ... more The effects of interconnection loss (both dc loss and skin effect loss) on crosstalk noise for a coupled lossy interconnection system, with various termination conditions, coupled lengths, spacings, and interconnection structures (microstrip lines versus strip lines) are investigated. Fourier transform techniques and numerical methods are applied to solve the coupled transmission line equations for the strong coupling case (mutual coupling between the active line and the quiet line). The interconnection is either terminated by its approximated matched load impedance, R,, or by the equivalent loading capacitance of the receiver, C L. General design guidelines for controlling the crosstalk noise and reflection noise in lossy interconnections are discussed.

Eleventh Annual International Phoenix Conference on Computers and Communication [1992 Conference Proceedings], 1992

Interconnection and packaging are among the dominant factors that limit the performance of future... more Interconnection and packaging are among the dominant factors that limit the performance of future integrated circuits containing millions of transistors. As chips become more complex, so does the packaging. Design automation is thus without doubt necessary. In this paper, a window based simulation environment called PDSE (Packaging Design Support Environment) which integrates several tools for VLSI interconnection modeling and simulations is presented. We will describe the concept of the automated packaging design cycle, the structure and the components of the simulation environment, and the implementation of an interconnect layout geometry data extractor. Finally a case study will be given to illustrate the entire design process.

Integration, 1994

The higher speed requirement and rising complexity of interconnect and packaging structure in a V... more The higher speed requirement and rising complexity of interconnect and packaging structure in a VLSI system have increased the necessity of applying modeling and simulation techniques to develop CAD tools for analysis and design. To effectively manage design data and CAD tools involved for modeling and simulation of electronic packaging, a framework which provides different levels of services and abstractions is essential. This paper describes a computer-aided design framework which provides three levels of services for the aforementioned purposes. The first level of the framework supports CAD tool integrations and simulation management. A common graphical user interface is provided for the simulation environment. In the second level, design data representation and management are stressed. We applied an object-oriented approach to develop design libraries and encapsulate CAD tools. The third level of the framework emphasizes system level modeling and simulation for multiple chip systems. The underlying architecture and implementation of the framework are explained, design examples given.

[1992 Proceedings] Electrical Performance of Electronic Packaging

In this paper, preliminary work on electrical performance estimation and evaluation for multi-chi... more In this paper, preliminary work on electrical performance estimation and evaluation for multi-chip assemblies (i.e., multi-chip modules , chip on board, and etc.) is presented. A knowledge base is built to facilitate system performance

IEEE Transactions on Advanced Packaging, 2000

A 133 MHz processor system bus (PSB) has been designed and developed for notebook computer system... more A 133 MHz processor system bus (PSB) has been designed and developed for notebook computer systems running at core frequency of 500 MHz and beyond based on an enhanced gunning transceiver logic. We described the design flow and highlighted the design challenges unique to notebook computers, It is shown that with careful I/O circuit design, transmission line analysis and reliability consideration, the design target can be achieved. A similar approach can be applied to notebook computers with even higher bus frequency.