Poul Williams - Academia.edu (original) (raw)

Papers by Poul Williams

Research paper thumbnail of Satisfiability checking using boolean expression diagrams

Research paper thumbnail of Unifying Two Formula Rewriting Techniques for Circuit Verification and Risk Assessment

Research paper thumbnail of IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. XX, NO. Y, MONTH 1999 1 Equivalence Checking of Combinational Circuits

The combinational logic-level equivalence problem is to determine whether two given combinational... more The combinational logic-level equivalence problem is to determine whether two given combinational circuits implement the same Boolean function. This problem arises in a number of CAD applications, for example when checking the correctness of incremental design changes (performed either manually or by a design automation tool).

Research paper thumbnail of Equivalence checking of hierarchical combinational circuits

ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357), 1999

Research paper thumbnail of Satisfiability checking using Boolean Expression Diagrams

International Journal on Software Tools for Technology Transfer (STTT), 2003

Research paper thumbnail of Equivalence checking of combinational circuits using Boolean expression diagrams

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1999

Research paper thumbnail of Formal Verification based on Boolean Expression Diagrams

Electronic Notes in Theoretical Computer Science, 2001

Research paper thumbnail of Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking

Lecture Notes in Computer Science, 2000

Research paper thumbnail of Satisfiability checking using boolean expression diagrams

Research paper thumbnail of Unifying Two Formula Rewriting Techniques for Circuit Verification and Risk Assessment

Research paper thumbnail of IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. XX, NO. Y, MONTH 1999 1 Equivalence Checking of Combinational Circuits

The combinational logic-level equivalence problem is to determine whether two given combinational... more The combinational logic-level equivalence problem is to determine whether two given combinational circuits implement the same Boolean function. This problem arises in a number of CAD applications, for example when checking the correctness of incremental design changes (performed either manually or by a design automation tool).

Research paper thumbnail of Equivalence checking of hierarchical combinational circuits

ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357), 1999

Research paper thumbnail of Satisfiability checking using Boolean Expression Diagrams

International Journal on Software Tools for Technology Transfer (STTT), 2003

Research paper thumbnail of Equivalence checking of combinational circuits using Boolean expression diagrams

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1999

Research paper thumbnail of Formal Verification based on Boolean Expression Diagrams

Electronic Notes in Theoretical Computer Science, 2001

Research paper thumbnail of Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking

Lecture Notes in Computer Science, 2000