Raghaw Rai - Academia.edu (original) (raw)
Papers by Raghaw Rai
EDFA Technical Articles
Localizing defects in one-of-a-kind failures can take days, weeks, or even months, after which a ... more Localizing defects in one-of-a-kind failures can take days, weeks, or even months, after which a detailed physical analysis is conducted to determine the root cause. TEM and STEM play complimentary roles in this process; TEM because of its superior spatial resolution and STEM because it produces images that are easier to interpret and is less susceptible to chromatic aberrations that can occur in thicker samples. In the past, the use of STEM in FA has been limited due to the time required to switch between imaging modes, but with the emergence of TEM/STEM microscopes with computer controlled lenses, the use of STEM is increasing. This article provides an overview of STEM techniques and present examples showing how it is used to characterize subtle and complex defects in ICs.
MRS Proceedings, 2002
The assessment of the thermal stability across HfO 2 /Si and HfO 2 /SiO 2 interfaces has been dif... more The assessment of the thermal stability across HfO 2 /Si and HfO 2 /SiO 2 interfaces has been difficult due to lack of thermodynamic data. In this paper, we present the results of thermodynamic calculations intended to fill this gap. A thermodynamic model was developed by assuming that HfSiO 4 is an ideal solution of HfO 2 and SiO 2 to a first order approximation. The theoretical results predict that the HfO 2 /Si interface is thermodynamically stable up to 1100°C, while the HfO 2 /SiO 2 interface is thermodynamically unstable even at room temperature. Our experimental results from TEM and XPS analysis are consistent with these modeling predictions.
Applied Physics Letters, 2002
ABSTRACT Polycrystalline-silicon (poly-Si) gate compatibility issues with HfO 2 and Al 2 O 3 capp... more ABSTRACT Polycrystalline-silicon (poly-Si) gate compatibility issues with HfO 2 and Al 2 O 3 capped HfO 2 gate dielectrics are reported. It can be generally stated that chemical vapor deposition (CVD) silicon gates using silane deposited directly onto HfO 2 results in electrical properties much worse compared to similar HfO 2 films using platinum metal gates. However, depositing CVD silicon gates directly onto Al 2 O 3 capped HfO 2 showed greater than a 104 times reduction in gate leakage compared to the poly-Si/HfO 2 and poly-Si/SiO 2 controls of similar electrical thickness. © 2002 American Institute of Physics.
2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), 2018
Developments in the semiconductor industry are driving the need for new methods to characterize s... more Developments in the semiconductor industry are driving the need for new methods to characterize smaller 3D devices in a productive and reproducible way. The automation of sample preparation, TEM imaging, and offline CD metrology is able to provide sample information in the form of both images and quantitative data. In this article, we evaluate the TEM imaging automation workflow in order to optimize the experimental configuration towards better measurement precision and higher throughput. It is found that the top contributor to CD precision is the signal-to-noise ratio of the STEM image, which is determined by the electron flux. We investigated the top 5 most important experimental factors (probe current, image size, dwell time, Drift Corrected Frame integration, and image Field of View) and their interactions for a secondary contributor to CD precision. And we found that the combination of those factors play very minor role as soon as they contribute to the same electron flux. This learning guides us to configure our experiment parameters to optimize the trade-off between measurement precision and throughput.
Device architectures incorporating multiple gate structures have been proposed to allow transisto... more Device architectures incorporating multiple gate structures have been proposed to allow transistor scaling beyond the planar MOSFET integrations. These device architectures can improve performance such as better short channel performance and reduced leakage. In addition the additional channel surface and gate electrodes offers new circuit possibilities such as dynamic threshold voltage control and an RF mixer are demonstrated. it is desirable to fabricate muiti-gated devices with the single gate on multiple sides and multiple gate electrodes this has been demonstrated successfully. lNruOOUCnON
We investigate the formation of CoSi 2 over a wide temperature range (275-450C for the first of a... more We investigate the formation of CoSi 2 over a wide temperature range (275-450C for the first of a 2-step formation), and show that, for a given anneal, it is possible to obtain significantly thicker silicides on poly than on substrate Si. By selecting appropriate time-temperature combinations, one can obtain thickness differences of 50% or more. This can be useful for obtaining low sheet resistance gates while minimizing silicide spiking in the junctions.
MRS Proceedings, 2002
As the MOSFET gate lengths are scaled down to 50 nm or below, the expected increase in gate leaka... more As the MOSFET gate lengths are scaled down to 50 nm or below, the expected increase in gate leakage will be countered by the use of a high dielectric constant (high K) material. The series capacitance from polysilicon gate electrode depletion significantly reduces the gate capacitance as the dielectric thickness is scaled down to 10 Å equivalent oxide thickness (EOT) or below. Metal gates promise to solve this problem and address other problems like boron penetration and enhanced gate resistance that will have increased focus as the polysilicon gate thickness is reduced. Extensive simulations have shown that the optimal gate work-functions for the sub-50 nm channel lengths should be 0.2 eV below (above) the conduction (valence) band edge of silicon for n-MOSFETs (p-MOSFETs). This study summarizes the evaluations of TiN, TaSiN, WN, TaN, TaSi, Ir and IrO2 as candidate metals for dual-metal gate CMOS using HfO2 as the gate dielectric. The gate work-function was determined by fabricatin...
MRS Proceedings, Dec 1, 2002
Decomposition experiments under corona discharge and theoretical calculations using the density f... more Decomposition experiments under corona discharge and theoretical calculations using the density functional theory (DFT) method were accomplished to clarify the dissociation behavior and decomposition mechanism of HFO1234zeE (trans-1,3,3,3-tetrafluoropropene), an eco-efficient SF 6 alternative gas. The discharge decomposition products of HFO are mainly fluorocarbon, unsaturated hydrocarbon and saturated hydrocarbons, which are containing no more than three carbons. Free radicals, CF 3 ,F, F,F and H$, generated via bond-cleavage reaction are important structures to promote the decomposition, and HFO is more likely to dissociate with them by abstraction reaction to form CF 4 and CF 3 H. Long-chain radicals, such as CF 3
Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 2003
As the metal–oxide–semiconductor field-effect transistor (MOSFET) gate lengths scale down to 50 n... more As the metal–oxide–semiconductor field-effect transistor (MOSFET) gate lengths scale down to 50 nm and below, the expected increase in gate leakage will be countered by the use of a high dielectric constant (high-gate oxide. The series capacitance from polysilicon gate ...
2003 IEEE Conference on Electron Devices and Solid-State Circuits (IEEE Cat. No.03TH8668)
A promising high k material, lanthanum aluminum oxynitride (LAON), with excellent material and el... more A promising high k material, lanthanum aluminum oxynitride (LAON), with excellent material and electronic properties is reported. The LAON film has good thermal stability and CMOS process compatibility at 1000 C. The LAON material has a dielectric constant of above 20, bandgap of 6.6 eV. Well-behaved I-V and C-V were obtained for 80 A LAON on silicon.
Microelectronic Engineering, 2003
Silicon gate compatibility problems with hafnium-based gate dielectrics are reported. It generall... more Silicon gate compatibility problems with hafnium-based gate dielectrics are reported. It generally can be stated that chemical vapor deposition (CVD) silicon gates using silane deposited directly onto polycrystalline HfO at conventional 2 temperatures (near 620 8C) results in (1) a low density of large inhomogeneous polycrystalline-silicon (poly-Si) grains, (2) electrical properties much worse compared to similar HfO films using metal gates or silicon gates with low temperature 2 deposition. However, depositing conventional CVD poly-Si gates directly onto Al O-capped, hafnium-silicate-capped, or 2 3 physical vapor deposition (PVD) silicon-capped HfO resulted in the absence of large inhomogeneous poly-Si grains and 2 3 well behaved capacitors with leakage reduction greater than 10 times compared to the poly-Si / HfO and poly-Si / SiO 2 2 controls of similar electrical thickness. The two observed adverse phenomena for conventional poly-Si deposited directly on HfO are attributed to a partial reduction of the HfO by the poly-Si deposition ambient. In the first case (1) the partial 2 2 reduction occurs locally on the HfO surface, forming Hf-Si bond(s) which act as nucleation points for crystalline silicon 2 x growth while in the second case (2) the partial reduction occurs along grain boundaries resulting in electrical traps that increase film leakage. In addition, it is postulated that similar adverse interactions with conventionally deposited CVD poly-Si may occur with any transition metal oxide whose metal can form stable silicides.
![Research paper thumbnail of Characteristics of atomic-layer-deposited thin Hf[sub x]Zr[sub 1−x]O[sub 2] gate dielectrics](https://attachments.academia-assets.com/91736514/thumbnails/1.jpg)
](Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 2007
In this study, the authors investigated the addition of zirconium ͑Zr͒ into HfO 2 to improve its ... more In this study, the authors investigated the addition of zirconium ͑Zr͒ into HfO 2 to improve its dielectric properties. Hf x Zr 1−x O 2 films were deposited by atomic-layer deposition at 200-350°C and annealed in a nitrogen ambient environment at 1000°C. Extensive physical characterization of the impact of alloying Zr into HfO 2 is studied using vacuum ultraviolet spectroscopy ellipsometry, attenuated total reflectance Fourier transform infrared spectroscopy, secondary-ion mass spectrometry, transmission electron microscopy, atomic force microscopy, x-ray diffraction, Rutherford backscattering spectrometry, and x-ray reflectometry. Hf x Zr 1−x O 2 transistors are fabricated to characterize the impact of Zr addition on electrical thickness, mobility, and reliability. Zr addition into HfO 2 leads to changes in film microstructure and grain-size distribution. Hf x Zr 1−x O 2 films have smaller and more uniform grain size compared to HfO 2 for all deposition temperatures explored here. As Zr content and deposition temperature are increased, stabilization of the tetragonal phase is observed. A monotonic decrease in band gap is observed as ZrO 2 content is increased. The chlorine impurity in the films is strongly dependent on deposition temperature and independent of film composition. TEM images of transistors showed excellent thermal stability as revealed by a sharp Hf x Zr 1−x O 2 / Si interface and no Zr silicide formation. Significant improvement in device properties such as lower electrical thickness ͑higher permittivities͒, lower threshold voltage ͑V t ͒ shift after stress ͑improved reliability͒, and higher mobilities are observed with Zr addition into HfO 2. All of these results show Hf x Zr 1−x O 2 to be a promising candidate for SiO 2 replacement.
Journal of The Electrochemical Society, 2003
ABSTRACT
![Research paper thumbnail of Theoretical and experimental investigation of boron diffusion in polycrystalline HfO[sub 2] films](https://attachments.academia-assets.com/91736512/thumbnails/1.jpg)
](Applied Physics Letters, 2002
Decomposition experiments under corona discharge and theoretical calculations using the density f... more Decomposition experiments under corona discharge and theoretical calculations using the density functional theory (DFT) method were accomplished to clarify the dissociation behavior and decomposition mechanism of HFO1234zeE (trans-1,3,3,3-tetrafluoropropene), an eco-efficient SF 6 alternative gas. The discharge decomposition products of HFO are mainly fluorocarbon, unsaturated hydrocarbon and saturated hydrocarbons, which are containing no more than three carbons. Free radicals, CF 3 ,F, F,F and H$, generated via bond-cleavage reaction are important structures to promote the decomposition, and HFO is more likely to dissociate with them by abstraction reaction to form CF 4 and CF 3 H. Long-chain radicals, such as CF 3
Top-down layer by layer delayering inspection with polisher and progressive cross-sectional Focus... more Top-down layer by layer delayering inspection with polisher and progressive cross-sectional Focus Ion Beam (XFIB) slicing are two common approaches for Physical Failure Analysis (PFA). This paper uses cross-sectional focus ion beam to perform top down layer by layer delayering inspection. The advantages of this technique include: 1) having a better control of the delayering progress 2) prevention of over-delayering and 3) having the ability to perform real time Scanning Electron Microscopy (SEM) view during top-down XFIB delayering to achieve a better understanding of the defect formation.
Current technology forecasts show that continued deep sub-micron device scaling will soon require... more Current technology forecasts show that continued deep sub-micron device scaling will soon require gate dielectrics to be thinned to much less than 1.5 nm EOT. To address this problem, high dielectric constant metal-oxide insulators are being extensively studied throughout the industry for use as gate dielectrics in ultra-scaled metal-oxide-semiconductor field-effect transistor (MOSFET) devices. However, incompatibilities of the desired MOSFET properties are observed with many of the dielectric systems and integration processes presently under investigation. Here we report on results related to integration of various metal-oxide high permittivity gate-dielectric stacks, including hafnium-based systems, into poly-silicon gated MOSFETs and capacitors.
Hafnium silicate gate dielectrics with SiO 2 compositions of 48-65 % were deposited using the tet... more Hafnium silicate gate dielectrics with SiO 2 compositions of 48-65 % were deposited using the tetrakisdiethylamino hafnium and tetrakisdimethylamino silicon precursors. MOSFETs were fabricated using a poly-Si-gate CMOS process and a gate leakage reduction of 28 X was obtained for a 13.3 A equivalent oxide thickness (EOT). The gate leakage current decreased as the amount of Hf in the film was increased. A subthreshold slope of 80-89 mV/decade was achieved. At the same CET inv , the normalized transconductance for 50 % SiO 2 silicate was lower than the 65 % SiO 2 silicate indicating a trade-off between the leakage reduction and the transconductance. The PMOS threshold voltages were higher than that of SiO 2 even when no channel implant was performed.
Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 2004
ABSTRACT In this article, we report film properties of HfO2 and La2O3 gate dielectrics grown on S... more ABSTRACT In this article, we report film properties of HfO2 and La2O3 gate dielectrics grown on Si(100) substrate using atomic layer deposition (ALD) with various surfaces modified before film growth. The precursors used for HfO2 and La2O3 films are hafnium tetrachloride (HfCl4), lanthanum tris[bis(trimethylsilyl)amide] (C18H54N3LaSi6) and water. Pre-deposition treatments examined for HfO2 dielectric films include (1) surface nitridation using NH3,N2O, or NO, (2) substrate annealing in an oxidizing or reducing ambient, and (3) surface fluorination. These results were compared to those obtained using established approaches of growing HfO2 on an OH terminated surface produced chemically. Linear film growth was observed for the HfO2 with all pre-deposition treatments. Time-of-flight-secondary ion mass spectrometry (TOF-SIMS) and transmission electron microscopy (TEM) analysis indicated that all pre-treatments result in good film coverage with no interaction between HfO2 and silicon at the silicon substrate. The as deposited ALD HfO2 film is mainly amorphous, continuous, and relatively smooth on all pretreated Si surface. The thickness of a thin interfacial layer varies depending on the particular pre-treatments. Similar studies were also conducted for the growt- - h of ALD La2O3. In this case, a significant interaction between La2O3 and silicon substrate was observed on films grown directly on chemical oxide. A rough interface between La2O3 and the silicon substrate is clearly seen in XTEM results. This interaction is more significant when the film is deposited at higher temperature. The XTEM images showed that the ALD La2O3 films are mostly amorphous. Results show that independent of surface pre-treatments, interactions between La2O3 and the silicon substrate occur for the deposition conditions explored here. Electrical characterization using evaporated platinum electrodes and mercury probe of the high-k film stacks have been carried out to determine the impact of the pre-treatments on the electrical properties of the films. Results indicated that ALD HfO2 films have higher dielectric constant, lower leakage and better flatband voltage stability during post deposition annealing compared to ALD La2O3 films. These results indicate that ALD HfO2 is a more promising candidate than ALD La2O3 due to superior thermal stability in contact with silicon. © 2004 American Vacuum Society.
… Inc., ECS SOI …, 2005
The semiconductor industry has scaled the MOSFET over the last decade using electrostatic scaling... more The semiconductor industry has scaled the MOSFET over the last decade using electrostatic scaling rules[1]. Manufacturing capabilities have made it feasible to scale the device structures to be shorter by advancing lithography, thinner dielectrics using more precise process ...
EDFA Technical Articles
Localizing defects in one-of-a-kind failures can take days, weeks, or even months, after which a ... more Localizing defects in one-of-a-kind failures can take days, weeks, or even months, after which a detailed physical analysis is conducted to determine the root cause. TEM and STEM play complimentary roles in this process; TEM because of its superior spatial resolution and STEM because it produces images that are easier to interpret and is less susceptible to chromatic aberrations that can occur in thicker samples. In the past, the use of STEM in FA has been limited due to the time required to switch between imaging modes, but with the emergence of TEM/STEM microscopes with computer controlled lenses, the use of STEM is increasing. This article provides an overview of STEM techniques and present examples showing how it is used to characterize subtle and complex defects in ICs.
MRS Proceedings, 2002
The assessment of the thermal stability across HfO 2 /Si and HfO 2 /SiO 2 interfaces has been dif... more The assessment of the thermal stability across HfO 2 /Si and HfO 2 /SiO 2 interfaces has been difficult due to lack of thermodynamic data. In this paper, we present the results of thermodynamic calculations intended to fill this gap. A thermodynamic model was developed by assuming that HfSiO 4 is an ideal solution of HfO 2 and SiO 2 to a first order approximation. The theoretical results predict that the HfO 2 /Si interface is thermodynamically stable up to 1100°C, while the HfO 2 /SiO 2 interface is thermodynamically unstable even at room temperature. Our experimental results from TEM and XPS analysis are consistent with these modeling predictions.
Applied Physics Letters, 2002
ABSTRACT Polycrystalline-silicon (poly-Si) gate compatibility issues with HfO 2 and Al 2 O 3 capp... more ABSTRACT Polycrystalline-silicon (poly-Si) gate compatibility issues with HfO 2 and Al 2 O 3 capped HfO 2 gate dielectrics are reported. It can be generally stated that chemical vapor deposition (CVD) silicon gates using silane deposited directly onto HfO 2 results in electrical properties much worse compared to similar HfO 2 films using platinum metal gates. However, depositing CVD silicon gates directly onto Al 2 O 3 capped HfO 2 showed greater than a 104 times reduction in gate leakage compared to the poly-Si/HfO 2 and poly-Si/SiO 2 controls of similar electrical thickness. © 2002 American Institute of Physics.
2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), 2018
Developments in the semiconductor industry are driving the need for new methods to characterize s... more Developments in the semiconductor industry are driving the need for new methods to characterize smaller 3D devices in a productive and reproducible way. The automation of sample preparation, TEM imaging, and offline CD metrology is able to provide sample information in the form of both images and quantitative data. In this article, we evaluate the TEM imaging automation workflow in order to optimize the experimental configuration towards better measurement precision and higher throughput. It is found that the top contributor to CD precision is the signal-to-noise ratio of the STEM image, which is determined by the electron flux. We investigated the top 5 most important experimental factors (probe current, image size, dwell time, Drift Corrected Frame integration, and image Field of View) and their interactions for a secondary contributor to CD precision. And we found that the combination of those factors play very minor role as soon as they contribute to the same electron flux. This learning guides us to configure our experiment parameters to optimize the trade-off between measurement precision and throughput.
Device architectures incorporating multiple gate structures have been proposed to allow transisto... more Device architectures incorporating multiple gate structures have been proposed to allow transistor scaling beyond the planar MOSFET integrations. These device architectures can improve performance such as better short channel performance and reduced leakage. In addition the additional channel surface and gate electrodes offers new circuit possibilities such as dynamic threshold voltage control and an RF mixer are demonstrated. it is desirable to fabricate muiti-gated devices with the single gate on multiple sides and multiple gate electrodes this has been demonstrated successfully. lNruOOUCnON
We investigate the formation of CoSi 2 over a wide temperature range (275-450C for the first of a... more We investigate the formation of CoSi 2 over a wide temperature range (275-450C for the first of a 2-step formation), and show that, for a given anneal, it is possible to obtain significantly thicker silicides on poly than on substrate Si. By selecting appropriate time-temperature combinations, one can obtain thickness differences of 50% or more. This can be useful for obtaining low sheet resistance gates while minimizing silicide spiking in the junctions.
MRS Proceedings, 2002
As the MOSFET gate lengths are scaled down to 50 nm or below, the expected increase in gate leaka... more As the MOSFET gate lengths are scaled down to 50 nm or below, the expected increase in gate leakage will be countered by the use of a high dielectric constant (high K) material. The series capacitance from polysilicon gate electrode depletion significantly reduces the gate capacitance as the dielectric thickness is scaled down to 10 Å equivalent oxide thickness (EOT) or below. Metal gates promise to solve this problem and address other problems like boron penetration and enhanced gate resistance that will have increased focus as the polysilicon gate thickness is reduced. Extensive simulations have shown that the optimal gate work-functions for the sub-50 nm channel lengths should be 0.2 eV below (above) the conduction (valence) band edge of silicon for n-MOSFETs (p-MOSFETs). This study summarizes the evaluations of TiN, TaSiN, WN, TaN, TaSi, Ir and IrO2 as candidate metals for dual-metal gate CMOS using HfO2 as the gate dielectric. The gate work-function was determined by fabricatin...
MRS Proceedings, Dec 1, 2002
Decomposition experiments under corona discharge and theoretical calculations using the density f... more Decomposition experiments under corona discharge and theoretical calculations using the density functional theory (DFT) method were accomplished to clarify the dissociation behavior and decomposition mechanism of HFO1234zeE (trans-1,3,3,3-tetrafluoropropene), an eco-efficient SF 6 alternative gas. The discharge decomposition products of HFO are mainly fluorocarbon, unsaturated hydrocarbon and saturated hydrocarbons, which are containing no more than three carbons. Free radicals, CF 3 ,F, F,F and H$, generated via bond-cleavage reaction are important structures to promote the decomposition, and HFO is more likely to dissociate with them by abstraction reaction to form CF 4 and CF 3 H. Long-chain radicals, such as CF 3
Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 2003
As the metal–oxide–semiconductor field-effect transistor (MOSFET) gate lengths scale down to 50 n... more As the metal–oxide–semiconductor field-effect transistor (MOSFET) gate lengths scale down to 50 nm and below, the expected increase in gate leakage will be countered by the use of a high dielectric constant (high-gate oxide. The series capacitance from polysilicon gate ...
2003 IEEE Conference on Electron Devices and Solid-State Circuits (IEEE Cat. No.03TH8668)
A promising high k material, lanthanum aluminum oxynitride (LAON), with excellent material and el... more A promising high k material, lanthanum aluminum oxynitride (LAON), with excellent material and electronic properties is reported. The LAON film has good thermal stability and CMOS process compatibility at 1000 C. The LAON material has a dielectric constant of above 20, bandgap of 6.6 eV. Well-behaved I-V and C-V were obtained for 80 A LAON on silicon.
Microelectronic Engineering, 2003
Silicon gate compatibility problems with hafnium-based gate dielectrics are reported. It generall... more Silicon gate compatibility problems with hafnium-based gate dielectrics are reported. It generally can be stated that chemical vapor deposition (CVD) silicon gates using silane deposited directly onto polycrystalline HfO at conventional 2 temperatures (near 620 8C) results in (1) a low density of large inhomogeneous polycrystalline-silicon (poly-Si) grains, (2) electrical properties much worse compared to similar HfO films using metal gates or silicon gates with low temperature 2 deposition. However, depositing conventional CVD poly-Si gates directly onto Al O-capped, hafnium-silicate-capped, or 2 3 physical vapor deposition (PVD) silicon-capped HfO resulted in the absence of large inhomogeneous poly-Si grains and 2 3 well behaved capacitors with leakage reduction greater than 10 times compared to the poly-Si / HfO and poly-Si / SiO 2 2 controls of similar electrical thickness. The two observed adverse phenomena for conventional poly-Si deposited directly on HfO are attributed to a partial reduction of the HfO by the poly-Si deposition ambient. In the first case (1) the partial 2 2 reduction occurs locally on the HfO surface, forming Hf-Si bond(s) which act as nucleation points for crystalline silicon 2 x growth while in the second case (2) the partial reduction occurs along grain boundaries resulting in electrical traps that increase film leakage. In addition, it is postulated that similar adverse interactions with conventionally deposited CVD poly-Si may occur with any transition metal oxide whose metal can form stable silicides.
Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 2007
In this study, the authors investigated the addition of zirconium ͑Zr͒ into HfO 2 to improve its ... more In this study, the authors investigated the addition of zirconium ͑Zr͒ into HfO 2 to improve its dielectric properties. Hf x Zr 1−x O 2 films were deposited by atomic-layer deposition at 200-350°C and annealed in a nitrogen ambient environment at 1000°C. Extensive physical characterization of the impact of alloying Zr into HfO 2 is studied using vacuum ultraviolet spectroscopy ellipsometry, attenuated total reflectance Fourier transform infrared spectroscopy, secondary-ion mass spectrometry, transmission electron microscopy, atomic force microscopy, x-ray diffraction, Rutherford backscattering spectrometry, and x-ray reflectometry. Hf x Zr 1−x O 2 transistors are fabricated to characterize the impact of Zr addition on electrical thickness, mobility, and reliability. Zr addition into HfO 2 leads to changes in film microstructure and grain-size distribution. Hf x Zr 1−x O 2 films have smaller and more uniform grain size compared to HfO 2 for all deposition temperatures explored here. As Zr content and deposition temperature are increased, stabilization of the tetragonal phase is observed. A monotonic decrease in band gap is observed as ZrO 2 content is increased. The chlorine impurity in the films is strongly dependent on deposition temperature and independent of film composition. TEM images of transistors showed excellent thermal stability as revealed by a sharp Hf x Zr 1−x O 2 / Si interface and no Zr silicide formation. Significant improvement in device properties such as lower electrical thickness ͑higher permittivities͒, lower threshold voltage ͑V t ͒ shift after stress ͑improved reliability͒, and higher mobilities are observed with Zr addition into HfO 2. All of these results show Hf x Zr 1−x O 2 to be a promising candidate for SiO 2 replacement.
Journal of The Electrochemical Society, 2003
ABSTRACT
Applied Physics Letters, 2002
Decomposition experiments under corona discharge and theoretical calculations using the density f... more Decomposition experiments under corona discharge and theoretical calculations using the density functional theory (DFT) method were accomplished to clarify the dissociation behavior and decomposition mechanism of HFO1234zeE (trans-1,3,3,3-tetrafluoropropene), an eco-efficient SF 6 alternative gas. The discharge decomposition products of HFO are mainly fluorocarbon, unsaturated hydrocarbon and saturated hydrocarbons, which are containing no more than three carbons. Free radicals, CF 3 ,F, F,F and H$, generated via bond-cleavage reaction are important structures to promote the decomposition, and HFO is more likely to dissociate with them by abstraction reaction to form CF 4 and CF 3 H. Long-chain radicals, such as CF 3
Top-down layer by layer delayering inspection with polisher and progressive cross-sectional Focus... more Top-down layer by layer delayering inspection with polisher and progressive cross-sectional Focus Ion Beam (XFIB) slicing are two common approaches for Physical Failure Analysis (PFA). This paper uses cross-sectional focus ion beam to perform top down layer by layer delayering inspection. The advantages of this technique include: 1) having a better control of the delayering progress 2) prevention of over-delayering and 3) having the ability to perform real time Scanning Electron Microscopy (SEM) view during top-down XFIB delayering to achieve a better understanding of the defect formation.
Current technology forecasts show that continued deep sub-micron device scaling will soon require... more Current technology forecasts show that continued deep sub-micron device scaling will soon require gate dielectrics to be thinned to much less than 1.5 nm EOT. To address this problem, high dielectric constant metal-oxide insulators are being extensively studied throughout the industry for use as gate dielectrics in ultra-scaled metal-oxide-semiconductor field-effect transistor (MOSFET) devices. However, incompatibilities of the desired MOSFET properties are observed with many of the dielectric systems and integration processes presently under investigation. Here we report on results related to integration of various metal-oxide high permittivity gate-dielectric stacks, including hafnium-based systems, into poly-silicon gated MOSFETs and capacitors.
Hafnium silicate gate dielectrics with SiO 2 compositions of 48-65 % were deposited using the tet... more Hafnium silicate gate dielectrics with SiO 2 compositions of 48-65 % were deposited using the tetrakisdiethylamino hafnium and tetrakisdimethylamino silicon precursors. MOSFETs were fabricated using a poly-Si-gate CMOS process and a gate leakage reduction of 28 X was obtained for a 13.3 A equivalent oxide thickness (EOT). The gate leakage current decreased as the amount of Hf in the film was increased. A subthreshold slope of 80-89 mV/decade was achieved. At the same CET inv , the normalized transconductance for 50 % SiO 2 silicate was lower than the 65 % SiO 2 silicate indicating a trade-off between the leakage reduction and the transconductance. The PMOS threshold voltages were higher than that of SiO 2 even when no channel implant was performed.
Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 2004
ABSTRACT In this article, we report film properties of HfO2 and La2O3 gate dielectrics grown on S... more ABSTRACT In this article, we report film properties of HfO2 and La2O3 gate dielectrics grown on Si(100) substrate using atomic layer deposition (ALD) with various surfaces modified before film growth. The precursors used for HfO2 and La2O3 films are hafnium tetrachloride (HfCl4), lanthanum tris[bis(trimethylsilyl)amide] (C18H54N3LaSi6) and water. Pre-deposition treatments examined for HfO2 dielectric films include (1) surface nitridation using NH3,N2O, or NO, (2) substrate annealing in an oxidizing or reducing ambient, and (3) surface fluorination. These results were compared to those obtained using established approaches of growing HfO2 on an OH terminated surface produced chemically. Linear film growth was observed for the HfO2 with all pre-deposition treatments. Time-of-flight-secondary ion mass spectrometry (TOF-SIMS) and transmission electron microscopy (TEM) analysis indicated that all pre-treatments result in good film coverage with no interaction between HfO2 and silicon at the silicon substrate. The as deposited ALD HfO2 film is mainly amorphous, continuous, and relatively smooth on all pretreated Si surface. The thickness of a thin interfacial layer varies depending on the particular pre-treatments. Similar studies were also conducted for the growt- - h of ALD La2O3. In this case, a significant interaction between La2O3 and silicon substrate was observed on films grown directly on chemical oxide. A rough interface between La2O3 and the silicon substrate is clearly seen in XTEM results. This interaction is more significant when the film is deposited at higher temperature. The XTEM images showed that the ALD La2O3 films are mostly amorphous. Results show that independent of surface pre-treatments, interactions between La2O3 and the silicon substrate occur for the deposition conditions explored here. Electrical characterization using evaporated platinum electrodes and mercury probe of the high-k film stacks have been carried out to determine the impact of the pre-treatments on the electrical properties of the films. Results indicated that ALD HfO2 films have higher dielectric constant, lower leakage and better flatband voltage stability during post deposition annealing compared to ALD La2O3 films. These results indicate that ALD HfO2 is a more promising candidate than ALD La2O3 due to superior thermal stability in contact with silicon. © 2004 American Vacuum Society.
… Inc., ECS SOI …, 2005
The semiconductor industry has scaled the MOSFET over the last decade using electrostatic scaling... more The semiconductor industry has scaled the MOSFET over the last decade using electrostatic scaling rules[1]. Manufacturing capabilities have made it feasible to scale the device structures to be shorter by advancing lithography, thinner dielectrics using more precise process ...