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Papers by Rajat Suvra Halder

Research paper thumbnail of Design and Simulation of Hybrid SET CMOS Based Sequential Circuit

International journal of computer science and informatics, Jul 1, 2013

Single Electron Transistor is a hot cake in the present research area of VLSI design and Microele... more Single Electron Transistor is a hot cake in the present research area of VLSI design and Microelectronics technology. It operates through one-by-one tunnelling of electrons through the channel, utilizing the Coulomb blockade Phenomenon. Due to nanoscale feature size, ultralow power dissipation, and unique Coulomb blockade oscillation characteristics it may replace Field Effect Transistor FET). SET is very much advantageous than CMOS in few points. And in few points CMOS is advantageous than SET. So it has been seen that Combination of SET and CMOS is very much effective in the nanoscale, low power VLSI circuits. This paper has given a idea to make different sequential circuits using the Hybrid SET-CMOS. The MIB model for SET and BSIM4 model for CMOS are used. The operations of the proposed circuits are verified in Tanner environment. The performances of CMOS and Hybrid SET-CMOS based circuits are compared. The hybrid SET-CMOS circuit is found to consume lesser power than the CMOS based circuit. Further it is established that hybrid SET-CMOS based circuit is much faster compared to CMOS based circuit.

Research paper thumbnail of Design and Simulation of Hybrid SET-CMOS based Hysteresis Circuits: Schmitt Trigger, with their Realization

Hybrid SET-CMOS circuits which combine the merits of both the SET [Single Electron Transistor] an... more Hybrid SET-CMOS circuits which combine the merits of both the SET [Single Electron Transistor] and CMOS promises to be a practical implementation for future low power ultradense VLSI/ULSI circuit design. In this work, an SET-CMOS hybrid hysteresis circuit is proposed. The MIB model for SET and BSIM4 model for CMOS are used. The operation of the proposed circuit is verified in Tanner environment.

Research paper thumbnail of Deep Learning based Detection of Foot Lift Event Using a Single Accelerometer for Accurate Firing of FES

Research paper thumbnail of EMG Based Clinical Evaluation of an Unpowered Exoskeleton Device

2023 IEEE International Symposium on Medical Measurements and Applications (MeMeA)

Research paper thumbnail of Impact of human intervention on assessing downstream channel behaviour of Ichamati River on the lower Gangetic Plain of West Bengal, India

Modeling Earth Systems and Environment, 2020

Since the period of human civilization, the hydrological and morphological characteristics of mos... more Since the period of human civilization, the hydrological and morphological characteristics of most of the rivers have been intensively modified by human interferences. In this context, the Ichamati River is one of the worst affected distributary channels flowing on the lower Gangetic delta of South Bengal. This tidally active river is streaming on the most densely inhabited district (North 24 Parganas) of West Bengal. The river is gradually decaying over time due to direct and indirect human activities on and along the river. Therefore, the prime aim of this research study is to explain the temporal change of the channel behaviour, especially fluvio-morphological characteristics of the river during 1976-2016. The present study also highlights location-specific causal factors liable for the downstream modification of the channel behaviour. In this research study, channel migration, erosion rate, bank vulnerability zone and channel planform pattern have been assessed using Landsat images of 1976, 1996 and 2016 in remote sensing and GIS environment. Besides, an intensive field survey was conducted for cross-sectional survey of the river. Primary data were gathered from brick kilns through a questionnaire survey for the estimation of sediment extraction rate from the river to prepare the sediment-water budget of the river. This study reveals that the morphological characteristics of Ichamati River have been modified at the human-nature interface and continuous siltation causes gradual upliftment of the riverbed. The channel is gradually narrowing and decaying over time. This study is helpful to understand the current status of the river and helps river scientists for its restoration as well as management planning.

Research paper thumbnail of A Microcontroller based Charge Balanced Trapezoidal Stimulus Generator for FES System

2021 IEEE International Instrumentation and Measurement Technology Conference (I2MTC)

Foot drop (FD) is the inability to lift the front part of the foot from the ground. It causes the... more Foot drop (FD) is the inability to lift the front part of the foot from the ground. It causes the toes to drag along the ground while walking and can cause fall and injuries. A patient may have FD when there is a loss of communication between the central nervous system and the peroneal nerve. It can be corrected by functional electrical stimulation (FES) of the peroneal nerve by applying pulses of a given duration, amplitude, and frequency. In this paper, we are proposing a microcontroller based FES system that produces trapezoidal, charge-balanced, biphasic stimulus output with near-zero DC level. In this design, we use a programmable ESP32 microcontroller with a built-in DAC, uniphasic to biphasic converter circuit, current amplifier and step-up transformer. Stimulation amplitude, pulse width and frequency of the stimulation pulse can easily be adjusted by using an adjustable knob. The cost of the overall system is very low and can be built using standard electronic components.

Research paper thumbnail of Analytical Modeling for Noise Margin Estimation of Nanoscale Hybrid SET-MOS Inverter Circuit

Research paper thumbnail of Design and Simulation of Hybrid SET-CMOS based Hysteresis Circuits: Schmitt Trigger, with their Realization

Hybrid SET-CMOS circuits which combine the merits of both the SET [Single Electron Transistor] an... more Hybrid SET-CMOS circuits which combine the merits of both the SET [Single Electron Transistor] and CMOS promises to be a practical implementation for future low power ultradense VLSI/ULSI circuit design. In this work, an SET-CMOS hybrid hysteresis circuit is proposed. The MIB model for SET and BSIM4 model for CMOS are used. The operation of the proposed circuit is verified in Tanner environment.

Research paper thumbnail of Design and Simulation of Hybrid SET CMOS Based Sequential Circuit

International Journal of Computer Science and Informatics, 2013

Single Electron Transistor is a hot cake in the present research area of VLSI design and Microele... more Single Electron Transistor is a hot cake in the present research area of VLSI design and Microelectronics technology. It operates through one-by-one tunnelling of electrons through the channel, utilizing the Coulomb blockade Phenomenon. Due to nanoscale feature size, ultralow power dissipation, and unique Coulomb blockade oscillation characteristics it may replace Field Effect Transistor FET). SET is very much advantageous than CMOS in few points. And in few points CMOS is advantageous than SET. So it has been seen that Combination of SET and CMOS is very much effective in the nanoscale, low power VLSI circuits. This paper has given a idea to make different sequential circuits using the Hybrid SET-CMOS. The MIB model for SET and BSIM4 model for CMOS are used. The operations of the proposed circuits are verified in Tanner environment. The performances of CMOS and Hybrid SET-CMOS based circuits are compared. The hybrid SET-CMOS circuit is found to consume lesser power than the CMOS ba...

Research paper thumbnail of Improvising limitations of DNN based ultrasound image reconstruction

Physical and Engineering Sciences in Medicine

Research paper thumbnail of Design and Simulation of Hybrid SET CMOS Based Sequential Circuit

International journal of computer science and informatics, Jul 1, 2013

Single Electron Transistor is a hot cake in the present research area of VLSI design and Microele... more Single Electron Transistor is a hot cake in the present research area of VLSI design and Microelectronics technology. It operates through one-by-one tunnelling of electrons through the channel, utilizing the Coulomb blockade Phenomenon. Due to nanoscale feature size, ultralow power dissipation, and unique Coulomb blockade oscillation characteristics it may replace Field Effect Transistor FET). SET is very much advantageous than CMOS in few points. And in few points CMOS is advantageous than SET. So it has been seen that Combination of SET and CMOS is very much effective in the nanoscale, low power VLSI circuits. This paper has given a idea to make different sequential circuits using the Hybrid SET-CMOS. The MIB model for SET and BSIM4 model for CMOS are used. The operations of the proposed circuits are verified in Tanner environment. The performances of CMOS and Hybrid SET-CMOS based circuits are compared. The hybrid SET-CMOS circuit is found to consume lesser power than the CMOS based circuit. Further it is established that hybrid SET-CMOS based circuit is much faster compared to CMOS based circuit.

Research paper thumbnail of Design and Simulation of Hybrid SET-CMOS based Hysteresis Circuits: Schmitt Trigger, with their Realization

Hybrid SET-CMOS circuits which combine the merits of both the SET [Single Electron Transistor] an... more Hybrid SET-CMOS circuits which combine the merits of both the SET [Single Electron Transistor] and CMOS promises to be a practical implementation for future low power ultradense VLSI/ULSI circuit design. In this work, an SET-CMOS hybrid hysteresis circuit is proposed. The MIB model for SET and BSIM4 model for CMOS are used. The operation of the proposed circuit is verified in Tanner environment.

Research paper thumbnail of Deep Learning based Detection of Foot Lift Event Using a Single Accelerometer for Accurate Firing of FES

Research paper thumbnail of EMG Based Clinical Evaluation of an Unpowered Exoskeleton Device

2023 IEEE International Symposium on Medical Measurements and Applications (MeMeA)

Research paper thumbnail of Impact of human intervention on assessing downstream channel behaviour of Ichamati River on the lower Gangetic Plain of West Bengal, India

Modeling Earth Systems and Environment, 2020

Since the period of human civilization, the hydrological and morphological characteristics of mos... more Since the period of human civilization, the hydrological and morphological characteristics of most of the rivers have been intensively modified by human interferences. In this context, the Ichamati River is one of the worst affected distributary channels flowing on the lower Gangetic delta of South Bengal. This tidally active river is streaming on the most densely inhabited district (North 24 Parganas) of West Bengal. The river is gradually decaying over time due to direct and indirect human activities on and along the river. Therefore, the prime aim of this research study is to explain the temporal change of the channel behaviour, especially fluvio-morphological characteristics of the river during 1976-2016. The present study also highlights location-specific causal factors liable for the downstream modification of the channel behaviour. In this research study, channel migration, erosion rate, bank vulnerability zone and channel planform pattern have been assessed using Landsat images of 1976, 1996 and 2016 in remote sensing and GIS environment. Besides, an intensive field survey was conducted for cross-sectional survey of the river. Primary data were gathered from brick kilns through a questionnaire survey for the estimation of sediment extraction rate from the river to prepare the sediment-water budget of the river. This study reveals that the morphological characteristics of Ichamati River have been modified at the human-nature interface and continuous siltation causes gradual upliftment of the riverbed. The channel is gradually narrowing and decaying over time. This study is helpful to understand the current status of the river and helps river scientists for its restoration as well as management planning.

Research paper thumbnail of A Microcontroller based Charge Balanced Trapezoidal Stimulus Generator for FES System

2021 IEEE International Instrumentation and Measurement Technology Conference (I2MTC)

Foot drop (FD) is the inability to lift the front part of the foot from the ground. It causes the... more Foot drop (FD) is the inability to lift the front part of the foot from the ground. It causes the toes to drag along the ground while walking and can cause fall and injuries. A patient may have FD when there is a loss of communication between the central nervous system and the peroneal nerve. It can be corrected by functional electrical stimulation (FES) of the peroneal nerve by applying pulses of a given duration, amplitude, and frequency. In this paper, we are proposing a microcontroller based FES system that produces trapezoidal, charge-balanced, biphasic stimulus output with near-zero DC level. In this design, we use a programmable ESP32 microcontroller with a built-in DAC, uniphasic to biphasic converter circuit, current amplifier and step-up transformer. Stimulation amplitude, pulse width and frequency of the stimulation pulse can easily be adjusted by using an adjustable knob. The cost of the overall system is very low and can be built using standard electronic components.

Research paper thumbnail of Analytical Modeling for Noise Margin Estimation of Nanoscale Hybrid SET-MOS Inverter Circuit

Research paper thumbnail of Design and Simulation of Hybrid SET-CMOS based Hysteresis Circuits: Schmitt Trigger, with their Realization

Hybrid SET-CMOS circuits which combine the merits of both the SET [Single Electron Transistor] an... more Hybrid SET-CMOS circuits which combine the merits of both the SET [Single Electron Transistor] and CMOS promises to be a practical implementation for future low power ultradense VLSI/ULSI circuit design. In this work, an SET-CMOS hybrid hysteresis circuit is proposed. The MIB model for SET and BSIM4 model for CMOS are used. The operation of the proposed circuit is verified in Tanner environment.

Research paper thumbnail of Design and Simulation of Hybrid SET CMOS Based Sequential Circuit

International Journal of Computer Science and Informatics, 2013

Single Electron Transistor is a hot cake in the present research area of VLSI design and Microele... more Single Electron Transistor is a hot cake in the present research area of VLSI design and Microelectronics technology. It operates through one-by-one tunnelling of electrons through the channel, utilizing the Coulomb blockade Phenomenon. Due to nanoscale feature size, ultralow power dissipation, and unique Coulomb blockade oscillation characteristics it may replace Field Effect Transistor FET). SET is very much advantageous than CMOS in few points. And in few points CMOS is advantageous than SET. So it has been seen that Combination of SET and CMOS is very much effective in the nanoscale, low power VLSI circuits. This paper has given a idea to make different sequential circuits using the Hybrid SET-CMOS. The MIB model for SET and BSIM4 model for CMOS are used. The operations of the proposed circuits are verified in Tanner environment. The performances of CMOS and Hybrid SET-CMOS based circuits are compared. The hybrid SET-CMOS circuit is found to consume lesser power than the CMOS ba...

Research paper thumbnail of Improvising limitations of DNN based ultrasound image reconstruction

Physical and Engineering Sciences in Medicine