Richa Sharma - Academia.edu (original) (raw)

Papers by Richa Sharma

Research paper thumbnail of FPGA implementation of AES encryption and decryption

… 2009. INCACEC 2009 …, 2009

Advanced Encryption Standard (AES), a Federal Information Processing Standard (FIPS), is an appro... more Advanced Encryption Standard (AES), a Federal Information Processing Standard (FIPS), is an approved cryptographic algorithm that can be used to protect electronic data. The AES can be programmed in software or built with pure hardware. However Field Programmable Gate Arrays (FPGAs) offer a quicker and more customizable solution. This paper presents the AES algorithm with regard to FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). ModelSim SE PLUS 5.7g software is used for simulation and optimization of the synthesizable VHDL code. Synthesizing and implementation (i.e. Translate, Map and Place and Route) of the code is carried out on Xilinx -Project Navigator, ISE 8.2i suite. All the transformations of both Encryption and Decryption are simulated using an iterative design approach in order to minimize the hardware consumption. Xilinx XC3S400 device of Spartan Family is used for hardware evaluation. This paper proposes a method to integrate the AES encrypter and the AES decrypter. This method can make it a very low-complexity architecture, especially in saving the hardware resource in implementing the AES (Inv) Sub Bytes module and (Inv) Mix columns module etc. Most designed modules can be used for both AES encryption and decryption. Besides, the architecture can still deliver a high data rate in both encryption/decryption operations. The proposed architecture is suited for hardware-critical applications, such as smart card, PDA, and mobile phone, etc.

Research paper thumbnail of Efficient AES implementations on ASICs and FPGAs

Research paper thumbnail of An FPGA Based Performance Analysis of Pipelining and Unrolling of AES Algorithm

… 2006. ADCOM 2006 …, 2006

Research paper thumbnail of A universal and efficient AES co-processor for field programmable logic arrays

Field Programmable Logic and Application, 2004

In this article we present a compact and efficient co-processor that calculates the Advanced Encr... more In this article we present a compact and efficient co-processor that calculates the Advanced Encryption Standard (AES). It implements the whole functionality of the AES algorithm: all key lengths (128-bit, 192-bit, and 256-bit) are supported for both, encryption and decryption. Furthermore, it supports the Cipher Block Chaining mode. Due to an innovative AES State representation the complete AES co-processor is well suited for low-end FPGAs. The integrated AMBA interface facilitates the integration of the co-processor in System-on-Chip designs too. An implementation on a Xilinx Virtex-E FPGA device uses only 1,125 CLB slices and no block RAMs. Our FPGA implementation reaches a throughput of 215 Mbps at a clock frequency of 161.0 MHz.

Research paper thumbnail of Implementation of JPEG 2000 MQ-Coder

... Mohamed Atri Department of Physics Faculty of Sciences Monastir, Tunisia Mohamed.Atri@fsm. rn... more ... Mohamed Atri Department of Physics Faculty of Sciences Monastir, Tunisia Mohamed.Atri@fsm. rnu.tn Rached Tourki Department of Physics Faculty of Sciences Monastir, Tunisia Rached.Tourki@planete.tn ... 3, pp 219-230, March 2003. [5] M.Ahmadvand, Omid Fatemi, Hossein ...

Research paper thumbnail of High throughput, low cost, fully pipelined architecture for AES crypto chip

… , 2006 Annual IEEE, 2006

Reprogrammable devices such as field programmable gate arrays (FPGA's) are highly attractive... more Reprogrammable devices such as field programmable gate arrays (FPGA's) are highly attractive options for hardware implementations of encryption algorithms. This paper proposes compact, memory less, high-speed hardware architectures for the Rijndael AES encryptor/decryptor, with combined data path, resource sharing and logic optimization for novel networking applications. Architectural optimization exploits the strength of pipelining, loop unrolling and sub-pipelining. Speed is increased

Research paper thumbnail of Implementation approaches for the advanced encryption standard algorithm

Circuits and Systems Magazine, IEEE, 2002

A bstract-This paper addresses various approaches for efficient hardware implementation of the Ad... more A bstract-This paper addresses various approaches for efficient hardware implementation of the Advanced Encryption Standard algorithm. The optimization methods can be divided into two classes: architectural optimization and algorithmic optimization. Architectural optimization exploits the strength of pipelining, loop unrolling and sub-pipelining. Speed is increased by processing multiple rounds simultaneously at the cost of increased area. Architectural optimization is not an effective solution in feedback mode. Loop unrolling is the only architecture that can achieve a slight speedup with significantly increased area. In non-feedback mode, subpipelining can achieve maximum speedup and the best speed/area ratio. Algorithmic optimization exploits algorithmic strength inside each round unit. Various methods to reduce the critical path and area of each round unit are presented. Resource sharing issues between encryptor and decryptor are also discussed. They become important issues when both encryptor and decryptor need to be implemented in a small area.

Research paper thumbnail of An AES crypto chip using a high-speed parallel pipelined architecture

Microprocessors and Microsystems, 2005

The number of Internet and wireless communications users has rapidly grown and that increases dem... more The number of Internet and wireless communications users has rapidly grown and that increases demand for security measures to protect user data transmitted over open channels. In December 2001, the National Institute of Standards and Technology (NIST) of the United States chose the Rijndael algorithm as the suitable Advanced Encryption Standard (AES) to replace the Data Encryption Standard (DES) algorithm. Since then, many hardware implementations have been proposed in literature. We present a hardware-efficient design increasing throughput for the AES algorithm using a high-speed parallel pipelined architecture. By using an efficient inter-round and intra-round pipeline design, our implementation achieves a high throughput of 29.77 Gbps in encryption whereas the highest throughput reported in literature is 21.54 Gbps.

Research paper thumbnail of Design and implementation of area optimized AES algorithm on reconfigurable FPGA

… , 2007. ICM 2007. …, 2007

Cryptography algorithms are becoming more necessary to ensure secure data transmission, which can... more Cryptography algorithms are becoming more necessary to ensure secure data transmission, which can be used in several applications. In this paper the hardware implementation of optimized area for the block cipher advanced encryption standard (AES-128) is introduced using field programmable gate array (FPGA). The core includes the key schedule expansion and storage, the encryption, the decryption, and 8-bit input/output data

Research paper thumbnail of Implementation of the AES-128 on Virtex-5 FPGAs

Progress in Cryptology– …, 2008

Research paper thumbnail of FPGA implementation of AES encryption and decryption

… 2009. INCACEC 2009 …, 2009

Advanced Encryption Standard (AES), a Federal Information Processing Standard (FIPS), is an appro... more Advanced Encryption Standard (AES), a Federal Information Processing Standard (FIPS), is an approved cryptographic algorithm that can be used to protect electronic data. The AES can be programmed in software or built with pure hardware. However Field Programmable Gate Arrays (FPGAs) offer a quicker and more customizable solution. This paper presents the AES algorithm with regard to FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). ModelSim SE PLUS 5.7g software is used for simulation and optimization of the synthesizable VHDL code. Synthesizing and implementation (i.e. Translate, Map and Place and Route) of the code is carried out on Xilinx -Project Navigator, ISE 8.2i suite. All the transformations of both Encryption and Decryption are simulated using an iterative design approach in order to minimize the hardware consumption. Xilinx XC3S400 device of Spartan Family is used for hardware evaluation. This paper proposes a method to integrate the AES encrypter and the AES decrypter. This method can make it a very low-complexity architecture, especially in saving the hardware resource in implementing the AES (Inv) Sub Bytes module and (Inv) Mix columns module etc. Most designed modules can be used for both AES encryption and decryption. Besides, the architecture can still deliver a high data rate in both encryption/decryption operations. The proposed architecture is suited for hardware-critical applications, such as smart card, PDA, and mobile phone, etc.

Research paper thumbnail of Efficient AES implementations on ASICs and FPGAs

Research paper thumbnail of An FPGA Based Performance Analysis of Pipelining and Unrolling of AES Algorithm

… 2006. ADCOM 2006 …, 2006

Research paper thumbnail of A universal and efficient AES co-processor for field programmable logic arrays

Field Programmable Logic and Application, 2004

In this article we present a compact and efficient co-processor that calculates the Advanced Encr... more In this article we present a compact and efficient co-processor that calculates the Advanced Encryption Standard (AES). It implements the whole functionality of the AES algorithm: all key lengths (128-bit, 192-bit, and 256-bit) are supported for both, encryption and decryption. Furthermore, it supports the Cipher Block Chaining mode. Due to an innovative AES State representation the complete AES co-processor is well suited for low-end FPGAs. The integrated AMBA interface facilitates the integration of the co-processor in System-on-Chip designs too. An implementation on a Xilinx Virtex-E FPGA device uses only 1,125 CLB slices and no block RAMs. Our FPGA implementation reaches a throughput of 215 Mbps at a clock frequency of 161.0 MHz.

Research paper thumbnail of Implementation of JPEG 2000 MQ-Coder

... Mohamed Atri Department of Physics Faculty of Sciences Monastir, Tunisia Mohamed.Atri@fsm. rn... more ... Mohamed Atri Department of Physics Faculty of Sciences Monastir, Tunisia Mohamed.Atri@fsm. rnu.tn Rached Tourki Department of Physics Faculty of Sciences Monastir, Tunisia Rached.Tourki@planete.tn ... 3, pp 219-230, March 2003. [5] M.Ahmadvand, Omid Fatemi, Hossein ...

Research paper thumbnail of High throughput, low cost, fully pipelined architecture for AES crypto chip

… , 2006 Annual IEEE, 2006

Reprogrammable devices such as field programmable gate arrays (FPGA's) are highly attractive... more Reprogrammable devices such as field programmable gate arrays (FPGA's) are highly attractive options for hardware implementations of encryption algorithms. This paper proposes compact, memory less, high-speed hardware architectures for the Rijndael AES encryptor/decryptor, with combined data path, resource sharing and logic optimization for novel networking applications. Architectural optimization exploits the strength of pipelining, loop unrolling and sub-pipelining. Speed is increased

Research paper thumbnail of Implementation approaches for the advanced encryption standard algorithm

Circuits and Systems Magazine, IEEE, 2002

A bstract-This paper addresses various approaches for efficient hardware implementation of the Ad... more A bstract-This paper addresses various approaches for efficient hardware implementation of the Advanced Encryption Standard algorithm. The optimization methods can be divided into two classes: architectural optimization and algorithmic optimization. Architectural optimization exploits the strength of pipelining, loop unrolling and sub-pipelining. Speed is increased by processing multiple rounds simultaneously at the cost of increased area. Architectural optimization is not an effective solution in feedback mode. Loop unrolling is the only architecture that can achieve a slight speedup with significantly increased area. In non-feedback mode, subpipelining can achieve maximum speedup and the best speed/area ratio. Algorithmic optimization exploits algorithmic strength inside each round unit. Various methods to reduce the critical path and area of each round unit are presented. Resource sharing issues between encryptor and decryptor are also discussed. They become important issues when both encryptor and decryptor need to be implemented in a small area.

Research paper thumbnail of An AES crypto chip using a high-speed parallel pipelined architecture

Microprocessors and Microsystems, 2005

The number of Internet and wireless communications users has rapidly grown and that increases dem... more The number of Internet and wireless communications users has rapidly grown and that increases demand for security measures to protect user data transmitted over open channels. In December 2001, the National Institute of Standards and Technology (NIST) of the United States chose the Rijndael algorithm as the suitable Advanced Encryption Standard (AES) to replace the Data Encryption Standard (DES) algorithm. Since then, many hardware implementations have been proposed in literature. We present a hardware-efficient design increasing throughput for the AES algorithm using a high-speed parallel pipelined architecture. By using an efficient inter-round and intra-round pipeline design, our implementation achieves a high throughput of 29.77 Gbps in encryption whereas the highest throughput reported in literature is 21.54 Gbps.

Research paper thumbnail of Design and implementation of area optimized AES algorithm on reconfigurable FPGA

… , 2007. ICM 2007. …, 2007

Cryptography algorithms are becoming more necessary to ensure secure data transmission, which can... more Cryptography algorithms are becoming more necessary to ensure secure data transmission, which can be used in several applications. In this paper the hardware implementation of optimized area for the block cipher advanced encryption standard (AES-128) is introduced using field programmable gate array (FPGA). The core includes the key schedule expansion and storage, the encryption, the decryption, and 8-bit input/output data

Research paper thumbnail of Implementation of the AES-128 on Virtex-5 FPGAs

Progress in Cryptology– …, 2008