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Papers by Richard Gu

Research paper thumbnail of Fractional-N phase locked loop design and applications

This paper presents fractional-N sigma-delta phase locked loop (PLL) applications and design. App... more This paper presents fractional-N sigma-delta phase locked loop (PLL) applications and design. Applications focus primarily on wireless communication and clock synthesizers. Fractional-N PLL architectures are described in detail. The performance of multi-stage noise shaping (MASH) and single-loop sigma-delta modulators is compared. Constraints on PLL loop bandwidth while using sigma-delta modulators is discussed. The causes of fractional spurs and spur reduction techniques are demonstrated.

Research paper thumbnail of High-Performance CML, ECL and NTL Bicmos Circuits

High-Performance Digital VLSI Circuit Design, 1996

Research paper thumbnail of 54 GHz CMOS LNAs with 3.6 dB NF and 28.2 dB gain using transformer feedback Gm-boosting technique

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2014

Research paper thumbnail of Low-phase-noise 54GHz quadrature VCO and 76GHz/90GHz VCOs in 65nm CMOS process

2014 IEEE Radio Frequency Integrated Circuits Symposium, 2014

This paper presents new circuit topologies and design techniques for low-phase-noise CMOS mmWave ... more This paper presents new circuit topologies and design techniques for low-phase-noise CMOS mmWave Quadrature VCO (QVCO) and VCOs. A transformer coupling with extra phase shift is proposed in QVCO to decouple the tradeoff between phase noise (PN) and phase error and improve the PN performance. This technique is demonstrated in a mmWave QVCO with a measured PN of -119.2dBc/Hz at 10MHz offset of a 56.2GHz carrier and a tuning range of 9.1% (FOM T of -179dBc/Hz). To our best knowledge, this QVCO has the lowest PN at 10MHz offset among all the QVCOs around 50-60GHz frequency range. In addition, an inductive divider feedback technique is proposed in VCO design to improve the transconductance linearity, resulting in larger signal swing and lower PN compared to the conventional LC VCOs. The effectiveness of this approach is demonstrated in a 76GHz VCO and a 90GHz VCO, both fabricated in a 65nm CMOS process, with an FOM T of 173.6dBc/Hz and 173.1dBc/Hz, respectively. Index Terms -VCO, quadrature VCO (QVCO), phase noise, transformer, transconductance linearization.

Research paper thumbnail of Fractional-N phase locked loop design and applications

This paper presents fractional-N sigma-delta phase locked loop (PLL) applications and design. App... more This paper presents fractional-N sigma-delta phase locked loop (PLL) applications and design. Applications focus primarily on wireless communication and clock synthesizers. Fractional-N PLL architectures are described in detail. The performance of multi-stage noise shaping (MASH) and single-loop sigma-delta modulators is compared. Constraints on PLL loop bandwidth while using sigma-delta modulators is discussed. The causes of fractional spurs and spur reduction techniques are demonstrated.

Research paper thumbnail of High-Performance CML, ECL and NTL Bicmos Circuits

High-Performance Digital VLSI Circuit Design, 1996

Research paper thumbnail of 54 GHz CMOS LNAs with 3.6 dB NF and 28.2 dB gain using transformer feedback Gm-boosting technique

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2014

Research paper thumbnail of Low-phase-noise 54GHz quadrature VCO and 76GHz/90GHz VCOs in 65nm CMOS process

2014 IEEE Radio Frequency Integrated Circuits Symposium, 2014

This paper presents new circuit topologies and design techniques for low-phase-noise CMOS mmWave ... more This paper presents new circuit topologies and design techniques for low-phase-noise CMOS mmWave Quadrature VCO (QVCO) and VCOs. A transformer coupling with extra phase shift is proposed in QVCO to decouple the tradeoff between phase noise (PN) and phase error and improve the PN performance. This technique is demonstrated in a mmWave QVCO with a measured PN of -119.2dBc/Hz at 10MHz offset of a 56.2GHz carrier and a tuning range of 9.1% (FOM T of -179dBc/Hz). To our best knowledge, this QVCO has the lowest PN at 10MHz offset among all the QVCOs around 50-60GHz frequency range. In addition, an inductive divider feedback technique is proposed in VCO design to improve the transconductance linearity, resulting in larger signal swing and lower PN compared to the conventional LC VCOs. The effectiveness of this approach is demonstrated in a 76GHz VCO and a 90GHz VCO, both fabricated in a 65nm CMOS process, with an FOM T of 173.6dBc/Hz and 173.1dBc/Hz, respectively. Index Terms -VCO, quadrature VCO (QVCO), phase noise, transformer, transconductance linearization.

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