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Papers by Audrey Roberto Silva

Journal of microelectromechanical systems, Aug 1, 2021

In this work, thermally evaporated aluminum (Al) was used as hardmask (HM) to obtain silicon micr... more In this work, thermally evaporated aluminum (Al) was used as hardmask (HM) to obtain silicon microchannels (SiMCs), using an Inductively Coupled Plasma - Reactive Ion Etching (ICP-RIE) system, in SF<sub>6</sub>/Ar gas mixture environment. The channel depth must be greater than <inline-formula> <tex-math notation="LaTeX">$50~\mu \text{m}$ </tex-math></inline-formula>, with a high aspect ratio. For this, Al HM lines were defined by photolithography and by Al wet etching on a silicon substrate. To improve the resistance against the ICP-RIE etching process, the Al HMs were treated with four different conditions: i) Al HM without treatment step (control sample); ii) with plasma nitridation (AlN/Al structure); iii) with thermal annealing (annealed Al film); iv) with plasma nitridation and annealing (annealed AlN/Al structure). After 100 min of ICP-RIE etching process, SiMC with depths of <inline-formula> <tex-math notation="LaTeX">$90.6~\mu \text{m}$ </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">$95~\mu \text{m}$ </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">$91.2~\mu \text{m}$ </tex-math></inline-formula>, and <inline-formula> <tex-math notation="LaTeX">$109~\mu \text{m}$ </tex-math></inline-formula>, respectively, were measured using a scan profiler system. As the main result, the annealed AlN/Al structure presented a high resistance against the ICP-RIE etching for 100 minutes. Furthermore, Scanning Electron Microscopy (SEM) images indicate an etch uniformity on the walls and bottom of the channels for all the samples. This parameter is a mandatory requirement to obtain the integrated microchannel liquid-cooling technology for heat sinks in photovoltaic cells and Complementary Metal-Oxide-Semiconductor microprocessors. [2021-0020]

Thin Solid Films, Nov 1, 2019

IEEE Journal of Photovoltaics, May 1, 2021

Periodic V-grooves channels, upright, and inverted pyramids structures were texturized on monocry... more Periodic V-grooves channels, upright, and inverted pyramids structures were texturized on monocrystalline silicon (c-Si) substrates using ammonium hydroxide (NH4OH) solution. This cheap and CMOS compatible etching solution aims at the integration of circuits with photovoltaic (PV) cells for monolithic purposes. To obtain these structures, lithographed silicon dioxide (SiO2) patterns were used to delimit the c-Si surface regions to be etched by the NH4OH solution. After the SiO2 removal, a scanning electron microscopy images of the surface of the samples showed that the NH4OH etch exposed the <111> facets, outlined by the SiO2 patterns, creating periodic V-groove channels, inverted, and upright pyramids structures with depths of 5.9 ± 0.1, 5.7 ± 0.4, and height of 6.9 ± 0.1 μm, respectively. These ordered structures reduced a polished c-Si control sample reflectance by 57.6 ± 0.1%, 53.3 ± 0.1%, and 51.6 ± 0.1%, measured by a spectrophotometer with integrating sphere and having reflectance values of 16.5%, 18.2%, and 18.9%, respectively. These results indicate that the etched periodic structures using a cheap and CMOS compatible NH4OH solution, increases the c-Si light trapping, by reducing its reflectance for values lower than 20%, which could be used to increase the light absorption on PV cells.

Junctionless-FET (JL-FET) devices were fabricated on SOI substrate using NH$_{\mathbf{4}}$ OH as ... more Junctionless-FET (JL-FET) devices were fabricated on SOI substrate using NH$_{\mathbf{4}}$ OH as means to thin the channel substrate. The devices gate dielectric was silicon oxynitride grown using O$_{\mathbf{2}} {/\mathbf{N}}_{\mathbf{2}}$ ECR (Electron-Cyclotron-Resonance) plasma, and its gate metal was TiN, which was defined by lift-off and deposited using reactive sputtering. The electrical contacts were fabricated with sputtered aluminum, defined by lift-off and sintered in conventional furnace. The final channel thickness was 63 nm, measured using SEM (Scanning Electron Microscopy) imaging. The channel dopant concentration was estimated at approximately 10$^{\mathbf{17}}\textbf{ atoms/cm}^{\mathbf{3}}$ based on the pseudo-MOS electrical measurements. JL-FET electrical measurements indicated the transistor behavior, despite the negative threshold voltage and the electrical contacts with high resistances. These results are as expected due to the measured channel thickness (of 63 nm) and the estimated channel dopant concentration (10$^{\mathbf{17}}\textbf{atoms/cm}^{\mathbf{3}}$). Furthermore, all Pseudo-MOS and JL-FET device measurements showed that the thinned channel is working very well, and that the silicon etching in NH$_{\mathbf{4}}$ OH solution is a viable technique to fabricate JL-FET devices.

ECS transactions, Sep 15, 2011

TaN films have been used as gate electrodes in MOS capacitors, which were fabricated with 18 nm t... more TaN films have been used as gate electrodes in MOS capacitors, which were fabricated with 18 nm thick SiO2 as gate dielectric, and in Schottky diodes on n-type Si (100) substrates. TaN layer presented electrical resistivity of 327 μΩ.cm and poly crystalline structure. MOS capacitors and Schottky diodes were sintered in conventional furnace in forming gas at 450 °C for different annealing times between 5 and 30 min. MOS Capacitors and Schottky diodes presented TaN/SiO2/Si/Al and TaN/Si/Al structures and were electrical characterized by capacitance-voltage (C-V) and current-voltage (I-V) measurements. From C-V measurements, the extracted TaN work function values and effective charge densities were between 3.9 and 4.4 eV, 1010 and 1012 cm-2, respectively. From I-V measurements, the work function values between 4.3 and 4.4 eV were extracted. Both devices present excellent results, which indicate that TaN electrodes can be used for MOS Technology and Schottky Diode.

Journal of vacuum science and technology, Jun 19, 2012

In this work, instead of TMAH (Tetra Methyl Ammonium Hydroxide), ammonium hydroxide (NH4OH) solut... more In this work, instead of TMAH (Tetra Methyl Ammonium Hydroxide), ammonium hydroxide (NH4OH) solutions are used to get silicon nano (SiNWs) or sub-micron (SiSMWs) wires, because also these solutions are silicon orientation-dependent wet etching and fully compatible with CMOS (Complementary Metal – Oxide - Semiconductor) technology.These wires were fabricated on Si and SOI (Silicon- On-Insulator) wafers, with (100) crystallographic orientation surfaces. On both wafers, the lateral etch rates under SiO2 of<110> plane Si wire sidewalls between 43 nm/min and 156 nm/min were obtained. Thus,SiNWs and SiSMWs were obtained, indicating that our NH4OH solution is a new alternative to get 3D structures on Si and SOI substrates. To confirm this result, pseudo-MOS (Metal-Oxide-Silicon) transistor on SOI substrate, with conduction channel of n+ Si wire of width of 1.22 μm and height of 100 nm, was fabricated. From drain-source current (IDS) versus back gate – source voltage (VBGS) curve of Pseudo MOS transistor, the threshold voltage (VT) of 1.36 V and the maximum transconductance of 20mumathrmS20 \mu \mathrm{S}20mumathrmS were extracted.

Resumos do..., Nov 30, 2019

2019 34th Symposium on Microelectronics Technology and Devices (SBMicro)

Junctionless-Field-Effect-Transistor (JL-FET) devices were fabricated with Silicon-On-Insulator (... more Junctionless-Field-Effect-Transistor (JL-FET) devices were fabricated with Silicon-On-Insulator (SOI) technology. The device channel area was thinned down to nanometer-scale by silicon etching in a solution of NH4 OH with the area to be exposed define using optical lithography and silicon oxide etching in HF buffer solution. The hardmask was stripped and dopant diffusion on a Phosphorus saturated furnace was carried out to achieve the dopant concentration necessary. The gate oxide was silicon oxide grown thermally in a dry environment. The electrical contacts were fabricated using optical lithography, silicon oxide etching in HF solution, aluminum sputtering and lift-off. The electrical contacts were annealed in forming gas (H2 + N2) for 10 minutes. Gate metal was titanium nitride deposited using sputtering and defined using optical lithography and lift-off. A layer of aluminum was deposited with the titanium nitride to protect it against oxidation. Some advantages were observed on this updated process. The outlines of the etched area are observable with optical microscopy in a dark field filter, making process confirmation easy. The same outlines are exposed for the majority of fabrication time, making atomic force microscopy (AFM) possible. Also, pseudo-MOS measurements are possible even before the gate metallization, which gives insight on the fabrication process and quality. The measurements on devices fully fabricated showed increasing control of the gate bias on the drain current, which is in agreement to JL-FET predictions, although these behave a gated resistor due to their negative threshold voltage. This happens because the mathrmVOH\mathrm{V}_{OH}mathrmVOH is high even for low a mathrmVGS\mathrm{V}_{GS}mathrmVGS, making the mathrmVDS\mathrm{V}_{DS}mathrmVDS needed to achieve saturation mode unmanageable. The electrical contacts were ohmic in nature and showed that the dopant diffusion process is compatible with JL-FET fabrication. Overall, these devices show that the JL-FET, and other nanometer-scaled structures, are possible to achieve using the channel thinning in NH4 OH solution silicon etching.

Orientador: José Alexandre DinizDissertação (mestrado) - Universidade Estadual de Campinas, Facul... more Orientador: José Alexandre DinizDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de ComputaçãoResumo: Este trabalho apresenta o desenvolvimento de células fotovoltaicas de junção n+/p em substratos de Si com processos de fabricação totalmente compatíveis com a tecnologia CMOS (Complementary Metal Oxide Semiconductor). Os processos compatíveis desenvolvidos neste trabalho sao as técnicas: i) de texturização da superfície do Si, com reflexao da superficie texturizada de 15% obtida com a formação de micro-pirâmides (alturas entre 3 e 7 ?m), utilizando-se solução alcalina de NH4OH (hidróxido de amônia), que e livre da contaminação indesejável por íons de Na+ e K+ quando se utiliza soluções tradicionais de NaOH e de KOH, respectivamente, e ii) de deposição ECR-CVD (Electron Cyclotron Resonance - Chemical Vapor Deposition) da camada antirrefletora (ARC) de SiNX (nitreto de silício), que e executada em temperatura ambiente, portanto pode ser fe...