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Papers by Senthil Ganesh Ramasamy

Research paper thumbnail of Design of high‐speed, low‐power, and area‐efficient FIR filters

IET Circuits, Devices & Systems, 2017

In a recent work, we have introduced a new multiple constant multiplication (MCM) algorithm, deno... more In a recent work, we have introduced a new multiple constant multiplication (MCM) algorithm, denoted as RADIX-2 r. The latter exhibits the best results in speed and power, comparatively with the most prominent algorithms. In this paper, the area aspect of RADIX-2 r is more specially investigated. RADIX-2 r is confronted to area efficient algorithms, notably to the cumulative benefit heuristic (Hcub) known for its lowest adder-cost. A number of benchmark FIR filters of growing complexity served for comparison. The results showed that RADIX-2 r is better than Hcub in area, especially for high order filters where the saving ranges from 1.50% up to 3.46%. This advantage is analytically proved and experimentally confirmed using a 65nm CMOS technology. Area efficiency is achieved along with important savings in speed and power, ranging from 6.37% up to 38.01% and from 9.30% up to 25.85%, respectively. When MCM blocks are implemented alone, the savings are higher: 10.18%, 47.24%, and 41.27% in area, speed, and power, respectively. Most importantly, we prove that MCM heuristics using similar addition pattern (A-operation with the same shift spans) as Hcub yield excessive bit-adder overhead in MCM problems of high complexity. As such, they are not competitive to RADIX-2 r in high order filters.

Research paper thumbnail of Design of High Speed, Low Power and Area Efficient 32-Bit Floating Point Multiplier

International Journal of Advance Engineering and Research Development, 2017

Digital arithmetic operations are the most important in the design of Digital Signal Processing (... more Digital arithmetic operations are the most important in the design of Digital Signal Processing (DSP) and Application Specific Integrated Circuit (ASIC) systems. Addition and Multiplication are the most basic arithmetic operations. Floating point (FP) multiplication is widely used in large set of scientific and signal processing computation. The speed of floating point arithmetic unit is very crucial performance parameter which impinges the operation of the system. A fast and accurate operation of a digital system is greatly influenced by the performance of different adders and multipliers using different methodology. Emerging trends in low power made attention towards the search of low power, high speed and area efficient adders and multipliers architecture. In this project, single precision (32-bit) floating point multiplier is designed. The main focus of this design is to reduce area, power and path delay to enhance the speed of the multiplication and addition operation. For floating point multiplier, Booth recoded multiplier is used where it reduces the number of partial products and thereby increase the speed of multiplication of the mantissa bits. For partial products addition, Carry Look-Ahead adder (CLA) and Kogge-Stone Adder (KSA) is implemented separately. The area, delay, power, speed, Power Delay Product (PDP) and Energy Delay Product (EDP) of two different implementation results are compared. Xilinx and ModelSim tool is used for simulation and VHDL coding for the design. Digital arithmetic operations are very important in the design of DSP and ASIC systems. Floating point computation has been widely used in graphics, digital signal processing, image processing and other applications. Floating point multiplication is a critical module in many applications especially for graphic processing unit, image recognition, navigation system in radar for identification, tracking & detection and 3D model. This type of complex application requires more time to process the data. Therefore, the high speed multiplication unit for floating point numbers is highly recommended to speed up multiplication process [4]. Multiplier output data size is twice than the input data size and therefore it consumes large chip area density, high complexity and time consuming process. Many different types of design models have been introduced to perform only for multiplication. Every design models have different multiplier and adder algorithms which perform the same operation but with different performance in terms of calculating speed and resource consumption. As the technology is improving, many researchers are trying to develop efficient multiplier designs which can offer high speed or low power or low area or the combination of all these three in single multiplier [4]. In this paper, radix-4 MBE algorithm is implemented for multiplication operation. This multiplier offers the advantage of both Booth algorithms. Booth algorithm is specially used for signed multiplication. It also reduces the number of partial products. The resource consumption of radix-4 MBE algorithm is less compared to the Wallace tree multiplier. In the existing system, CLA is used for partial product addition. The proposed system uses the same radix-4 MBE for partial product generation and Parallel Prefix Adders (PPA) such as KSA is used for partial product addition. PPA offers highly efficient solution to the binary addition and suitable for VLSI implementations. II. IEEE FLOATING POINT REPRESENTATION In the early stage, fixed point representation was the easiest method to convert the real numbers to binary because fixed-point representation adheres to the same basic arithmetic principles as integers. Fixed point representation has limited range of values and exceeding the limit can cause data overflow. The floating point number is nothing but the radix point (decimal point) can be placed anywhere relative to the significant digits of the number. In general, floating point representations are slower and less accurate than fixed point representations. It has better precision and support a much wider range of values. The size of the floating point representation that can be stored is either 32-bit (single precision) or 64-bit (double precision) defined by IEEE 754 standard [5].

Research paper thumbnail of Design of high‐speed, low‐power, and area‐efficient FIR filters

IET Circuits, Devices & Systems, 2017

In a recent work, we have introduced a new multiple constant multiplication (MCM) algorithm, deno... more In a recent work, we have introduced a new multiple constant multiplication (MCM) algorithm, denoted as RADIX-2 r. The latter exhibits the best results in speed and power, comparatively with the most prominent algorithms. In this paper, the area aspect of RADIX-2 r is more specially investigated. RADIX-2 r is confronted to area efficient algorithms, notably to the cumulative benefit heuristic (Hcub) known for its lowest adder-cost. A number of benchmark FIR filters of growing complexity served for comparison. The results showed that RADIX-2 r is better than Hcub in area, especially for high order filters where the saving ranges from 1.50% up to 3.46%. This advantage is analytically proved and experimentally confirmed using a 65nm CMOS technology. Area efficiency is achieved along with important savings in speed and power, ranging from 6.37% up to 38.01% and from 9.30% up to 25.85%, respectively. When MCM blocks are implemented alone, the savings are higher: 10.18%, 47.24%, and 41.27% in area, speed, and power, respectively. Most importantly, we prove that MCM heuristics using similar addition pattern (A-operation with the same shift spans) as Hcub yield excessive bit-adder overhead in MCM problems of high complexity. As such, they are not competitive to RADIX-2 r in high order filters.

Research paper thumbnail of Design of High Speed, Low Power and Area Efficient 32-Bit Floating Point Multiplier

International Journal of Advance Engineering and Research Development, 2017

Digital arithmetic operations are the most important in the design of Digital Signal Processing (... more Digital arithmetic operations are the most important in the design of Digital Signal Processing (DSP) and Application Specific Integrated Circuit (ASIC) systems. Addition and Multiplication are the most basic arithmetic operations. Floating point (FP) multiplication is widely used in large set of scientific and signal processing computation. The speed of floating point arithmetic unit is very crucial performance parameter which impinges the operation of the system. A fast and accurate operation of a digital system is greatly influenced by the performance of different adders and multipliers using different methodology. Emerging trends in low power made attention towards the search of low power, high speed and area efficient adders and multipliers architecture. In this project, single precision (32-bit) floating point multiplier is designed. The main focus of this design is to reduce area, power and path delay to enhance the speed of the multiplication and addition operation. For floating point multiplier, Booth recoded multiplier is used where it reduces the number of partial products and thereby increase the speed of multiplication of the mantissa bits. For partial products addition, Carry Look-Ahead adder (CLA) and Kogge-Stone Adder (KSA) is implemented separately. The area, delay, power, speed, Power Delay Product (PDP) and Energy Delay Product (EDP) of two different implementation results are compared. Xilinx and ModelSim tool is used for simulation and VHDL coding for the design. Digital arithmetic operations are very important in the design of DSP and ASIC systems. Floating point computation has been widely used in graphics, digital signal processing, image processing and other applications. Floating point multiplication is a critical module in many applications especially for graphic processing unit, image recognition, navigation system in radar for identification, tracking & detection and 3D model. This type of complex application requires more time to process the data. Therefore, the high speed multiplication unit for floating point numbers is highly recommended to speed up multiplication process [4]. Multiplier output data size is twice than the input data size and therefore it consumes large chip area density, high complexity and time consuming process. Many different types of design models have been introduced to perform only for multiplication. Every design models have different multiplier and adder algorithms which perform the same operation but with different performance in terms of calculating speed and resource consumption. As the technology is improving, many researchers are trying to develop efficient multiplier designs which can offer high speed or low power or low area or the combination of all these three in single multiplier [4]. In this paper, radix-4 MBE algorithm is implemented for multiplication operation. This multiplier offers the advantage of both Booth algorithms. Booth algorithm is specially used for signed multiplication. It also reduces the number of partial products. The resource consumption of radix-4 MBE algorithm is less compared to the Wallace tree multiplier. In the existing system, CLA is used for partial product addition. The proposed system uses the same radix-4 MBE for partial product generation and Parallel Prefix Adders (PPA) such as KSA is used for partial product addition. PPA offers highly efficient solution to the binary addition and suitable for VLSI implementations. II. IEEE FLOATING POINT REPRESENTATION In the early stage, fixed point representation was the easiest method to convert the real numbers to binary because fixed-point representation adheres to the same basic arithmetic principles as integers. Fixed point representation has limited range of values and exceeding the limit can cause data overflow. The floating point number is nothing but the radix point (decimal point) can be placed anywhere relative to the significant digits of the number. In general, floating point representations are slower and less accurate than fixed point representations. It has better precision and support a much wider range of values. The size of the floating point representation that can be stored is either 32-bit (single precision) or 64-bit (double precision) defined by IEEE 754 standard [5].