S S KERUR - Academia.edu (original) (raw)

Papers by S S KERUR

Journal of Engineering Education Transformations

Technology is an ever-advancing field at par with scientific and technological innovations. Techn... more Technology is an ever-advancing field at par with scientific and technological innovations. Technical higher education policy always tries to adopt and implement these changes in their scheme and curriculum in line with industry requirements. The present paper briefs about the latest indications on the teaching/learning methods and technical change in academia of countries on the path of development, and its effects in the applying the enhanced employment of students in core industries. Here the tool for successful enhancing of employment in related industry over the years is discussed. Exploration of the corporate working environment with focused design orientation is addressed through specific industry guided projects. The proposed plan of industry supported (Prakalp) projects are implemented at our institution, starting from pre-final year to final year UG scheme over past three years. Key benefits observed through the implementation of the proposed scheme are enhanced employment of students in related industries, improved skill development of the students and peer learning among student fraternity through group discussions. Industry guided projects can help to reduce the technological gap between industry and academia. Teaching fraternity can communicate in progressive and meaningful way with team of students and industry mentors for the implementation of set objectives of the projects.

International journal of engineering research and technology, Jul 20, 2021

Micro-Electronics and Telecommunication Engineering, 2022

A multiplier is one of the most important building block that is widely used in processor, embedd... more A multiplier is one of the most important building block that is widely used in processor, embedded, VLSI applications, Application specific integrated circuits and most of the DSP applications. The three main thrust parameters of any VLSI design lies in speed, area and power. Low power is an emerging trend which intern can maximize the lifespan of battery operating time. In this paper an attempt is made to balance and optimize the performance of Wallace multiplier which consumes less power. The two main sources of power consumption are static power dissipation and dynamic power dissipation. The multiplier has been designed and simulated using various VLSI techniques. The 1 International Journal of Pure and Applied Mathematics Volume 120 No. 6 2018, 767-785 ISSN: 1314-3395 (on-line version) url: http://www.acadpubl.eu/hub/ Special Issue http://www.acadpubl.eu/hub/

Short for Arithmetic Logic Unit, ALU is one of the important components within a computer process... more Short for Arithmetic Logic Unit, ALU is one of the important components within a computer processor. It performs arithmetic functions like addition, subtraction, multiplication, division etc along with logical functions. Pipelining allows execution of multiple instructions simultaneously. Pipelined ALU gives better performance which will evaluated in terms of number of clock cycles required in performing each arithmetic operation. Floating point representation is based on IEEE standard 754. In this paper a pipelined ALU is proposed simulating five arithmetic operations namely addition, subtraction, multiplication, division and square root in the HDL environment. Simulation Results is also obtained in IP Core Generator supported by Xilinx. Synthesis is carried out on the Xilinx 13.2 platform and ISim is used for the simulation process.

International Journal of Engineering and Advanced Technology, 2020

In gift scenario each method has to be compelled to be quick, adept and simple. Fast Fourier tran... more In gift scenario each method has to be compelled to be quick, adept and simple. Fast Fourier transform (FFT) may be a competent algorithmic program to calculate the N purpose Discrete Fourier transform (DFT).It has huge applications in communication systems, signal processing and image processing and instrumentation. However the accomplishment of FFT needs immense range of complicated multiplications, therefore to create this method quick and simple. It’s necessary for a number to be quick and power adept. To influence this problem the mixture of Urdhva Tiryagbhyam associate degreed Karatsuba algorithmic program offers is an adept technique of multiplication [1]. Vedic arithmetic is that the aboriginal system of arithmetic that includes a distinctive technique of calculation supported sixteen Sutras. Using these techniques within the calculation algorithms of the coprocessor can reduce the complexness, execution time, area, power etc. The distinctiveness during this project is Fast ...

The design of integrated circuits will change a lot because of shorter time-to-market it is impos... more The design of integrated circuits will change a lot because of shorter time-to-market it is impossible to design all functional blocks from scratch. One proposed solution to this problem is to use Network-On-Chip (NOC) architectures,[18] which are built up from reusable interconnect IP blocks. In NOC 2D mesh is popular due to its simple implementation and scalability of simple XY routing, but due to long network diameter and extra hops makes it energy inefficient as the network grows on the other part Extended diametrical 2D mesh architecture reduces the network diameter up to 50 percent compared to 2D mesh at the cost of few extra links added to the architecture. Router is the main building block in NOC architecture and Router with XY algorithm is well known for its simplicity. In this project XY algorithm is changed to Extended XY algorithm where an extra diametrical link will be used which will reduce the number of hops considerably and helps in performance enhancement.

The Close-range photogrammetric and Computer vision relies on image processing techniques in orde... more The Close-range photogrammetric and Computer vision relies on image processing techniques in order to obtain the information required for tasks devoted to perceiving, sensing and measuring the world around a machine vision system. Corners are the principal local features in image. In general, they are nothing but the points that may have highcurvature and appear in the intersection of various brightness sections of images. In several image attributes, edges are not altered by means of illumination and those attributes have the feature of rotating invariance. They account only about minimal of 0.05% in the total pixels. These have to be either identified or extracted without sacrificing image information.

International journal of scientific research in science, engineering and technology, Jun 30, 2016

The aim of this paper is to give briefing of the concept of network-on-chip (NoC). NoC is an appr... more The aim of this paper is to give briefing of the concept of network-on-chip (NoC). NoC is an approach to design the communication subsystem between IP cores in a System on Chip (SoC). NoCs can span synchronous and asynchronous clock domains or use unclocked asynchronous logic. This NoC brings an effective improvement over conventional busses and cross bar switches. The power requirement of the SoC is high where as it can be reduced by the NoC architecture. NoC is an developing paper in the field of VLSI. Since the use of emerging NoC architecture in VLSI it reduces the size of the architecture due to the reduced amount of buses and transmission lines. ." In a NoC system, modules such as processor cores, memories and specialized IP blocks exchange data using a network as a "public transportation" sub-system for the information traffic. The wires in the links of the NoC are shared by many signals

Lecture Notes in Networks and Systems, 2022

Kalmeshwar N. Hosur, Girish V. Attimarad , Harish M. Kittur , S. S. Kerur #4 # Department of Elec... more Kalmeshwar N. Hosur, Girish V. Attimarad , Harish M. Kittur , S. S. Kerur #4 # Department of Electronics & Communication Engg., S.D.M. College of Engineering & Technology, Dharwad, Karnataka, India, 1 kalmeshwar.hosur@gmail.com kerurss@gmail.com * Department of Electronics & Communication Engg., Dayanand Sagar College of Engineering, Kumarswamy Layout, Bangalore, Karnataka, India, shreyagiri@rediffmail.com School of Electrical Sciences, VIT University, Vellore, Tamilnadu, India . harish13579@rediffmail.com

Image processing has an important role in signal processing. The occurrence of noise in the image... more Image processing has an important role in signal processing. The occurrence of noise in the image can degrade its quality and can cause loss of information. In this paper, design of Gaussian, mean, and median filters is considered. Gaussian and mean filters are linear filters and are designed using convolution between 3 × 3 image pixel matrix and kernel matrix. The median filter is a nonlinear filter. An SRAM-based FPGA implementation of such a filter is susceptible to memory bit flips that are caused by single-event upsets (SEUs). Hence, a protection method is needed to ensure proper working of the median filter. Here, the median filter design proposed in (Aranda et al. in J. IEEE Transactions on Nuclear Science 64:2219–2226, 2017 [7]) is used to check if the median value obtained is within a dynamic range. The performance of these three filters is evaluated by considering image quality metrics such as PSNR and correlation coefficient with four different noises. The results show ch...

Lecture Notes in Electrical Engineering, 2018

In this paper, the designing and analysis of 10-bit, 2 MS/s Successive Approximation ADC using no... more In this paper, the designing and analysis of 10-bit, 2 MS/s Successive Approximation ADC using nonredundant SAR and Split DAC is described. Simulation is performed through Cadence tool using gpdk 180 nm technology. Dynamic range for this architecture is 60.19 dB. The charge redistribution DAC in split capacitor structure has a total capacitance which is 96.87% lesser compared to a usual design. To construct 10-bit successive approximation register analog-to-digital converter (SAR ADC), there are two successive approximation register (SAR) configurations are used. First one is sequencer code register successive approximation register configuration, which needs 20 FFs and thus desires more power consumption and occupies more area. The second one is nonredundant successive approximation register configuration, which needs 10 FFs and some combinational logic, thus requires less power consumption and occupies less area. Hence successive approximation registers ADC implementation using sp...

Bonfring International Journal of Research in Communication Engineering, 2016

A RNS reverse convertor moduli set {2p+1,2p,2p-1} is proposed in this paper. Chinese Remainder Th... more A RNS reverse convertor moduli set {2p+1,2p,2p-1} is proposed in this paper. Chinese Remainder Theorem is simplified to get a reverse converter that uses mod-{2p-1} operations. The proposed architecture reduces the burden of explicit use of moduli operation in conversion process and we prove that theoretically speaking it outperforms state of the art equivalent converters. In order to restrict the range we makes use of radix-8 booth modified rns multiplier in the proposed converter on cyclone2 FPGA. When compare to other convertors, this architecture saves power, area, delay and cost .

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS), 2014