Said Hamdioui - Academia.edu (original) (raw)

Papers by Said Hamdioui

Research paper thumbnail of Panel session what is the electronics industry doing to win the battle against the expected scary failure rates in future technology nodes?

2013 18TH IEEE EUROPEAN TEST SYMPOSIUM (ETS), 2013

ABSTRACT The major bottleneck for technology scaling is the growing rate of hardware failures. Pr... more ABSTRACT The major bottleneck for technology scaling is the growing rate of hardware failures. Process variations are becoming extreme and sensitivity to radiation is becoming severe. In addition, intrinsic failures such as device parameter degradation are accelerating the wear-out. All of these are leading to higher random in-filed failures and shorter device lifetime. The 2011 ITRS (International Technology Roadmap for Semiconductors) projects very high bit failure rates of the order of 10−2 for SRAM and of 10−3 for latches for 16nm high performance technology. Hence, solving reliability challenges for future technologies requires new efficient and cost effective approaches not only to detect and recover from in-filed failures, but also to extend the device lifetime for targeted applications. The panel session aims at gathering opinions from electronics industry on the above challenges and discuss some strategic approaches to provide resilience against intrinsic, random and extrinsic failures. Some questions we hope to be answered are: • Is the electronics industry already facing any reliability issues? How big is the problem? • What is the industry using today to realize reliable and robust systems? Is this going to changes soon? • Can reliability problems prevent using smaller technology nodes in run-time and safety critical applications? • How is reliability evaluation done today? Are there any tools? • Are reliability problems going to become server with technology scaling? Can we quantify? • What is industry doing to prepare themselves and prevent the scary expected failure rates? • Do they need a deep understanding of the technology in order to provide efficient solutions? • What is the best approach to use (bottom-up or top-down)? • Etc.

Research paper thumbnail of Comparison of Reaction-Diffusion and Atomistic Trap-Based BTI Models for Logic Gates

IEEE Transactions on Device and Materials Reliability, 2000

In deeply scaled CMOS technology, time-dependent degradation mechanisms (TDDMs), such as Bias Tem... more In deeply scaled CMOS technology, time-dependent degradation mechanisms (TDDMs), such as Bias Temperature Instability (BTI), have threatened the transistor performance, hence the overall circuit/system reliability. Two well-known attempts to model BTI mechanism are the reaction-diffusion (R-D) model and the Atomistic trap-based model. This paper presents a thorough comparative analysis of the two models at the gate-level in order to explore when their predictions are the same and when not. The comparison is done by evaluating degradation trends in a set of CMOS logic gates (e.g., INV, NAND, NOR, etc.) while considering seven attributes: 1) gate type, 2) gate drive strength, 3) input frequency, 4) duty factor, 5) non-periodicity, 6) instant degradation versus long-term aging, and 7) simulation CPU time and memory usage. The simulation results show that two models are in consistency in terms of the gate degradation trends w.r.t. the first four attributes (gate type, input frequency, etc.). For the rest of the attributes, the workload-dependent solution of the Atomistic trap-based model is superior from the point of non-periodicity and instant degradation, while the R-D model gets advantageous in case of long-term aging, and simulation CPU time and memory usage due to its lite AC periodic and duty factor dependent solution.

Research paper thumbnail of Panel session what is the electronics industry doing to win the battle against the expected scary failure rates in future technology nodes?

2013 18TH IEEE EUROPEAN TEST SYMPOSIUM (ETS), 2013

ABSTRACT The major bottleneck for technology scaling is the growing rate of hardware failures. Pr... more ABSTRACT The major bottleneck for technology scaling is the growing rate of hardware failures. Process variations are becoming extreme and sensitivity to radiation is becoming severe. In addition, intrinsic failures such as device parameter degradation are accelerating the wear-out. All of these are leading to higher random in-filed failures and shorter device lifetime. The 2011 ITRS (International Technology Roadmap for Semiconductors) projects very high bit failure rates of the order of 10−2 for SRAM and of 10−3 for latches for 16nm high performance technology. Hence, solving reliability challenges for future technologies requires new efficient and cost effective approaches not only to detect and recover from in-filed failures, but also to extend the device lifetime for targeted applications. The panel session aims at gathering opinions from electronics industry on the above challenges and discuss some strategic approaches to provide resilience against intrinsic, random and extrinsic failures. Some questions we hope to be answered are: • Is the electronics industry already facing any reliability issues? How big is the problem? • What is the industry using today to realize reliable and robust systems? Is this going to changes soon? • Can reliability problems prevent using smaller technology nodes in run-time and safety critical applications? • How is reliability evaluation done today? Are there any tools? • Are reliability problems going to become server with technology scaling? Can we quantify? • What is industry doing to prepare themselves and prevent the scary expected failure rates? • Do they need a deep understanding of the technology in order to provide efficient solutions? • What is the best approach to use (bottom-up or top-down)? • Etc.

Research paper thumbnail of Panel session what is the electronics industry doing to win the battle against the expected scary failure rates in future technology nodes?

2013 18TH IEEE EUROPEAN TEST SYMPOSIUM (ETS), 2013

ABSTRACT The major bottleneck for technology scaling is the growing rate of hardware failures. Pr... more ABSTRACT The major bottleneck for technology scaling is the growing rate of hardware failures. Process variations are becoming extreme and sensitivity to radiation is becoming severe. In addition, intrinsic failures such as device parameter degradation are accelerating the wear-out. All of these are leading to higher random in-filed failures and shorter device lifetime. The 2011 ITRS (International Technology Roadmap for Semiconductors) projects very high bit failure rates of the order of 10−2 for SRAM and of 10−3 for latches for 16nm high performance technology. Hence, solving reliability challenges for future technologies requires new efficient and cost effective approaches not only to detect and recover from in-filed failures, but also to extend the device lifetime for targeted applications. The panel session aims at gathering opinions from electronics industry on the above challenges and discuss some strategic approaches to provide resilience against intrinsic, random and extrinsic failures. Some questions we hope to be answered are: • Is the electronics industry already facing any reliability issues? How big is the problem? • What is the industry using today to realize reliable and robust systems? Is this going to changes soon? • Can reliability problems prevent using smaller technology nodes in run-time and safety critical applications? • How is reliability evaluation done today? Are there any tools? • Are reliability problems going to become server with technology scaling? Can we quantify? • What is industry doing to prepare themselves and prevent the scary expected failure rates? • Do they need a deep understanding of the technology in order to provide efficient solutions? • What is the best approach to use (bottom-up or top-down)? • Etc.

Research paper thumbnail of Comparison of Reaction-Diffusion and Atomistic Trap-Based BTI Models for Logic Gates

IEEE Transactions on Device and Materials Reliability, 2000

In deeply scaled CMOS technology, time-dependent degradation mechanisms (TDDMs), such as Bias Tem... more In deeply scaled CMOS technology, time-dependent degradation mechanisms (TDDMs), such as Bias Temperature Instability (BTI), have threatened the transistor performance, hence the overall circuit/system reliability. Two well-known attempts to model BTI mechanism are the reaction-diffusion (R-D) model and the Atomistic trap-based model. This paper presents a thorough comparative analysis of the two models at the gate-level in order to explore when their predictions are the same and when not. The comparison is done by evaluating degradation trends in a set of CMOS logic gates (e.g., INV, NAND, NOR, etc.) while considering seven attributes: 1) gate type, 2) gate drive strength, 3) input frequency, 4) duty factor, 5) non-periodicity, 6) instant degradation versus long-term aging, and 7) simulation CPU time and memory usage. The simulation results show that two models are in consistency in terms of the gate degradation trends w.r.t. the first four attributes (gate type, input frequency, etc.). For the rest of the attributes, the workload-dependent solution of the Atomistic trap-based model is superior from the point of non-periodicity and instant degradation, while the R-D model gets advantageous in case of long-term aging, and simulation CPU time and memory usage due to its lite AC periodic and duty factor dependent solution.

Research paper thumbnail of Panel session what is the electronics industry doing to win the battle against the expected scary failure rates in future technology nodes?

2013 18TH IEEE EUROPEAN TEST SYMPOSIUM (ETS), 2013

ABSTRACT The major bottleneck for technology scaling is the growing rate of hardware failures. Pr... more ABSTRACT The major bottleneck for technology scaling is the growing rate of hardware failures. Process variations are becoming extreme and sensitivity to radiation is becoming severe. In addition, intrinsic failures such as device parameter degradation are accelerating the wear-out. All of these are leading to higher random in-filed failures and shorter device lifetime. The 2011 ITRS (International Technology Roadmap for Semiconductors) projects very high bit failure rates of the order of 10−2 for SRAM and of 10−3 for latches for 16nm high performance technology. Hence, solving reliability challenges for future technologies requires new efficient and cost effective approaches not only to detect and recover from in-filed failures, but also to extend the device lifetime for targeted applications. The panel session aims at gathering opinions from electronics industry on the above challenges and discuss some strategic approaches to provide resilience against intrinsic, random and extrinsic failures. Some questions we hope to be answered are: • Is the electronics industry already facing any reliability issues? How big is the problem? • What is the industry using today to realize reliable and robust systems? Is this going to changes soon? • Can reliability problems prevent using smaller technology nodes in run-time and safety critical applications? • How is reliability evaluation done today? Are there any tools? • Are reliability problems going to become server with technology scaling? Can we quantify? • What is industry doing to prepare themselves and prevent the scary expected failure rates? • Do they need a deep understanding of the technology in order to provide efficient solutions? • What is the best approach to use (bottom-up or top-down)? • Etc.