Samira Sayedsalehi - Academia.edu (original) (raw)
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Papers by Samira Sayedsalehi
International Journal of Industrial Electronics, Control and Optimization (IECO), 2022
Quantum-dot Cellular Automata (QCA) is a new technology for eliminating some of the problems of e... more Quantum-dot Cellular Automata (QCA) is a new technology for eliminating some of the problems of existing technologies such as CMOS. Some of the key advantages of QCA are an intersection of wires in the same plane, high speed, small area, power consumption, complexity and low cost. Employing a three-input majority gate, a five-input majority gate and three logic gates, this study presents a full-adder circuit in a single layer which for higher efficiency and avoiding much complexity and based on the function of the intended full-adder circuit, the five-input gate is proposed. The proposed full-adder circuit and the proposed ripple adder circuit are compared with previous designs regarding complexity, number of cells, and area and the results are reported. Moreover, proposed circuits' power consumption has been calculated by using QCApro. These results indicate that the proposed full adder design in comparison with previous similar design achieved 36%, 20% and 4.4% reduction in the number of cells, latency and power consumption, respectively.
International Journal of Industrial Electronics, Control and Optimization (IECO), 2022
Quantum-dot Cellular Automata (QCA) is a new technology for eliminating some of the problems of e... more Quantum-dot Cellular Automata (QCA) is a new technology for eliminating some of the problems of existing technologies such as CMOS. Some of the key advantages of QCA are an intersection of wires in the same plane, high speed, small area, power consumption, complexity and low cost. Employing a three-input majority gate, a five-input majority gate and three logic gates, this study presents a full-adder circuit in a single layer which for higher efficiency and avoiding much complexity and based on the function of the intended full-adder circuit, the five-input gate is proposed. The proposed full-adder circuit and the proposed ripple adder circuit are compared with previous designs regarding complexity, number of cells, and area and the results are reported. Moreover, proposed circuits' power consumption has been calculated by using QCApro. These results indicate that the proposed full adder design in comparison with previous similar design achieved 36%, 20% and 4.4% reduction in the number of cells, latency and power consumption, respectively.