Sani Nassif - Academia.edu (original) (raw)
Papers by Sani Nassif
Springer eBooks, Dec 10, 2020
Design, Automation, and Test in Europe, Mar 12, 2012
Design Automation Conference, Jun 13, 2005
Design Automation Conference, Jul 24, 2006
Proceedings of ESSCIRC, Sep 1, 2007
Our ability to reliably predict the outcome of a semiconductor manufacturing process has been ste... more Our ability to reliably predict the outcome of a semiconductor manufacturing process has been steadily deteriorating. This is happening because of two important factors. First, the overall CMOS technology slowdown has led to rapidly increasing complexity in the process and in its interaction with design. This has in turn caused an increase in the number and magnitude of systematic sources of mismatch between simulation models (both at the technology-CAD and at the circuit simulation levels) and hardware measurements. Second, manufacturing variability resulting from random as well as systematic phenomena -long a source of concern only for analog design- is becoming important for digital design as well and thus its prediction is now a first order priority. Process complexity and the challenges of accurately modeling variability have conspired to increase the error in performance predictions, leading to a gap in model to hardware matching. In this paper, we will review these issues and show examples of potential solutions to this problem some of which are currently being developed in IBM, and some which are longer term and would benefit greatly from the attention of the academic community
IEEE Solid-State Circuits Magazine, 2019
International Conference on Computer Aided Design, Nov 4, 2001
Modern sub-micron VLSI designs include huge power grids that are required to distribute large amo... more Modern sub-micron VLSI designs include huge power grids that are required to distribute large amounts of current, at increasingly lower voltages. The resulting voltage drop on the grid reduces noise margin and increases gate delay, resulting in a serious performance impact. Checking the integrity of the supply voltage using traditional circuit simulation is not practical, for reasons of time and memory complexity. We propose a novel multigrid-like technique for the analysis of power grids. The grid is reduced to a coarser structure, and the solution is mapped back to the original grid. Experimental results show that the proposed method is very efficient as well as suitable for both DC and transient analysis of power grids.
Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455), Nov 13, 2002
Auerbach Publications eBooks, Nov 12, 2008
On-Chip SRAMs are an integral part of safety-critical System-on-Chips. At the same time however, ... more On-Chip SRAMs are an integral part of safety-critical System-on-Chips. At the same time however, they are also most susceptible to reliability threats such as Bias Temperature Instability (BTI), originating from the continuous trend of technology shrinking. BTI leads to a significant performance degradation, especially in the Sense Amplifiers (SAs) of SRAMs, where failures are fatal, since the data of a whole column is destroyed. As BTI strongly depends on the workload of an application, the aging rates of SAs in a memory array differ significantly and the incorporation of workload information into aging simulations is vital. Especially in safety-critical systems precise estimation of application specific reliability requirements to predict the memory lifetime is a key concern. In this paper we present a workload-aware aging analysis for On-Chip SRAMs that incorporates the workload of real applications executed on a processor. According to this workload, we predict the performance degradation of the SAs in the memory. We integrate this aging analysis into an aging-aware SRAM design exploration framework that generates and characterizes memories of different array granularity to select the most reliable memory architecture for the intended application. We show that this technique can mitigate SA degradation significantly depending on the environmental conditions and the application workload.
Symposium on Integrated Circuits and Systems Design, Jan 30, 1998
ABSTRACT
Springer eBooks, Dec 10, 2020
Design, Automation, and Test in Europe, Mar 12, 2012
Design Automation Conference, Jun 13, 2005
Design Automation Conference, Jul 24, 2006
Proceedings of ESSCIRC, Sep 1, 2007
Our ability to reliably predict the outcome of a semiconductor manufacturing process has been ste... more Our ability to reliably predict the outcome of a semiconductor manufacturing process has been steadily deteriorating. This is happening because of two important factors. First, the overall CMOS technology slowdown has led to rapidly increasing complexity in the process and in its interaction with design. This has in turn caused an increase in the number and magnitude of systematic sources of mismatch between simulation models (both at the technology-CAD and at the circuit simulation levels) and hardware measurements. Second, manufacturing variability resulting from random as well as systematic phenomena -long a source of concern only for analog design- is becoming important for digital design as well and thus its prediction is now a first order priority. Process complexity and the challenges of accurately modeling variability have conspired to increase the error in performance predictions, leading to a gap in model to hardware matching. In this paper, we will review these issues and show examples of potential solutions to this problem some of which are currently being developed in IBM, and some which are longer term and would benefit greatly from the attention of the academic community
IEEE Solid-State Circuits Magazine, 2019
International Conference on Computer Aided Design, Nov 4, 2001
Modern sub-micron VLSI designs include huge power grids that are required to distribute large amo... more Modern sub-micron VLSI designs include huge power grids that are required to distribute large amounts of current, at increasingly lower voltages. The resulting voltage drop on the grid reduces noise margin and increases gate delay, resulting in a serious performance impact. Checking the integrity of the supply voltage using traditional circuit simulation is not practical, for reasons of time and memory complexity. We propose a novel multigrid-like technique for the analysis of power grids. The grid is reduced to a coarser structure, and the solution is mapped back to the original grid. Experimental results show that the proposed method is very efficient as well as suitable for both DC and transient analysis of power grids.
Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455), Nov 13, 2002
Auerbach Publications eBooks, Nov 12, 2008
On-Chip SRAMs are an integral part of safety-critical System-on-Chips. At the same time however, ... more On-Chip SRAMs are an integral part of safety-critical System-on-Chips. At the same time however, they are also most susceptible to reliability threats such as Bias Temperature Instability (BTI), originating from the continuous trend of technology shrinking. BTI leads to a significant performance degradation, especially in the Sense Amplifiers (SAs) of SRAMs, where failures are fatal, since the data of a whole column is destroyed. As BTI strongly depends on the workload of an application, the aging rates of SAs in a memory array differ significantly and the incorporation of workload information into aging simulations is vital. Especially in safety-critical systems precise estimation of application specific reliability requirements to predict the memory lifetime is a key concern. In this paper we present a workload-aware aging analysis for On-Chip SRAMs that incorporates the workload of real applications executed on a processor. According to this workload, we predict the performance degradation of the SAs in the memory. We integrate this aging analysis into an aging-aware SRAM design exploration framework that generates and characterizes memories of different array granularity to select the most reliable memory architecture for the intended application. We show that this technique can mitigate SA degradation significantly depending on the environmental conditions and the application workload.
Symposium on Integrated Circuits and Systems Design, Jan 30, 1998
ABSTRACT