Saurabh Chaudhury - Academia.edu (original) (raw)

Papers by Saurabh Chaudhury

Authorea (Authorea), Jun 6, 2022

On pure and metal, non-metal, co-doped rutile TiO2, DFT simulations are performed. For the stabil... more On pure and metal, non-metal, co-doped rutile TiO2, DFT simulations are performed. For the stability study of doped materials, the defect formation energies of non-metal (S), metal (Fe), and metal and non-metal (Fe/S) co-doped materials are determined. A Ti-rich environment is preferable over an O-rich environment. With values of 2.98 eV, 2.18 eV, 1.58 eV, and 1.40 eV, the bandgap for pristine, S-doped, Fe-doped, and Fe/S co-doped materials is found to be direct. The effective masses (m*) and ratios (R) of charge carriers are also examined, and it is discovered that Fe/S co-doped material has the lowest charge carrier recombination rate. The maximum static dielectric constant is found in the Fe/S co-doped material. Doped material's

Journal of Electronic Materials, Jul 6, 2023

2022 IEEE 6th Conference on Information and Communication Technology (CICT), Nov 18, 2022

Nanomaterials, 2019

We report the results of a computational study of TiO2 nanoclusters of various sizes as well as o... more We report the results of a computational study of TiO2 nanoclusters of various sizes as well as of complex systems with various molecules adsorbed onto the clusters to set the ground for the modeling of charge transfer processes in hybrid organic–inorganic photovoltaics or photocatalytic degradation of pollutants. Despite the large number of existing computational studies of TiO2 clusters and in spite of the higher computing power of the typical available hardware, allowing for calculations of larger systems, there are still studies that use cluster sizes that are too small and not appropriate to address particular problems or certain complex systems relevant in photovoltaic or photocatalytic applications. By means of density functional theory (DFT) calculations, we attempt to find acceptable minimal sizes of the TinO2n+2H4 (n = 14, 24, 34, 44, 54) nanoclusters in correlation with the size of the adsorbed molecule and the rigidity of the backbone of the molecule to model systems and...

Journal of Applied Physics, 2008

Ab initio electronic-structure calculations were performed by using density functional theory wit... more Ab initio electronic-structure calculations were performed by using density functional theory with polarized basis set (LanL2DZ) within the spin polarized generalized gradient approximation for metal (M=Ti,Zr,Hf) doped Sin clusters where n varies from 9 to 20. In the first step of the calculation, geometrical optimizations of the nanoclusters have been done. In the next step, these optimized geometries have been used to calculate the binding energy (BE) and HOMO-LUMO gap (ΔEg) of the clusters. In order to check the stability of the clusters, the second order energy differences of the optimized geometries have been calculated. To study the optical behavior of the clusters, IR and Raman spectra calculation have been done. Further calculations on cation and anion clusters have been done to obtain their ionization potential (IP), electron affinity (EA), and chemical potential.

International Journal of System Assurance Engineering and Management

Canadian Journal of Physics, Dec 1, 2011

ABSTRACT A number of graphite–clay composites with varying percentages of graphite in the clay ho... more ABSTRACT A number of graphite–clay composites with varying percentages of graphite in the clay host have been prepared and their AC conductivities and dielectric behaviours have been studied in the frequency range from 42 Hz to 5 MHz. Measurements have been done for various concentrations of graphite filler to characterize their behaviour and develop composites with the desired conductivity for possible practical applications. The AC conductivity, σ(ω), increased with ω and followed a power law σ(ω) ωs with s ≤ 1, signifying conduction by hopping mechanism. The dielectric behaviour and loss tangents of the samples have been characterized by loss peaks for all of the samples, suggesting the presence of relaxation dipoles. The broad asymmetric loss peaks of the dielectric response were analyzed using the Havriliak–Negami function and associated parameters relaxation time, τ; broadening, γ; and asymmetry, β, have been obtained.

Scientia Iranica, Mar 5, 2019

This paper investigates the structural stability and electronic properties of titanium dioxide (T... more This paper investigates the structural stability and electronic properties of titanium dioxide (TiO 2) nanowires of di erent novel shapes using rst-principle-based density functional approach. Among linear, ladder, saw tooth, square, triangular, hexagonal, and octahedron shaped atomic con gurations, the ladder shape is the most energetically stable. After computation of lattice parameters as well as various mechanical properties of nanowire TiO2, it was observed that the highest bulk modulus was related to triangular TiO2 nanowire, which showed the highest mechanical strength of structure, whereas hexagonal con guration had the lowest bulk modulus, showing the lowest mechanical strength of structure. Analysis of various electronic properties showed that di erent con gurations of TiO2 nanowires could have di erent utilities as solid-state materials.

IGI Global eBooks, 2018

Multilevel thresholding is a popular image segmentation technique. However, computational complex... more Multilevel thresholding is a popular image segmentation technique. However, computational complexityofmultilevelthresholdingincreasesveryrapidlywithincreasingnumberofthresholds. Metaheuristicalgorithmsareappliedtoreducecomputationalcomplexityofmultilevelthresholding. AnewmethodofmultilevelthresholdingbasedonMoth-FlameOptimization(MFO)algorithmis proposedinthispaper.ThegoodnessofthethresholdsisevaluatedusingKapur'sentropyorOtsu's betweenclassvariancefunction.Theproposedmethodistestedonasetofbenchmarktestimagesand theperformanceiscomparedwithPSO(ParticleSwarmOptimization)andBFO(BacterialForaging Optimization)basedmethods.Theresultsareanalyzedobjectivelyusingthefitnessfunctionand thePeakSignaltoNoiseRatio(PSNR)values.ItisfoundthatMFObasedmultilevelthresholding methodperformsbetterthanthePSOandBFObasedmethods.

CRC Press eBooks, Apr 4, 2023

IGI Global eBooks, Sep 9, 2022

Multilevelthresholdingiswidelyusedinbrainmagneticresonance(MR)imagesegmentation.In thisarticle,am... more Multilevelthresholdingiswidelyusedinbrainmagneticresonance(MR)imagesegmentation.In thisarticle,amultilevelthresholding-basedbrainMRimagesegmentationtechniqueisproposed. Theimageisfirstfilteredusinganisotropicdiffusion.Thenmultilevelthresholdingbasedonparticle swarmoptimization(PSO)isperformedonthefilteredimagetogetthefinalsegmentedimage.Otsu functionisusedtoselectthethresholds.TheproposedtechniqueiscomparedwithstandardPSO andbacterialforagingoptimization(BFO)basedmultilevelthresholdingtechniques.Theobjective imagequalitymetricssuchasPeakSignaltoNoiseRatio(PSNR)andMeanStructuralSIMilarity (MSSIM)indexareusedtoevaluatethequalityofthesegmentedimages.Theexperimentalresults suggestthattheproposedtechniquegivessignificantlybetter-qualityimagesegmentationcompared totheothertechniqueswhenappliedtoT2-weitghtedbrainMRimages.

2022 IEEE 10th Region 10 Humanitarian Technology Conference (R10-HTC)

Applied Physics A, 2020

To remove simultaneously the ambipolar conduction and enhance HF performances, we propose a promi... more To remove simultaneously the ambipolar conduction and enhance HF performances, we propose a promising configuration of DG-TFET with asymmetric gate–drain overlap (ASGDO DG-TFET) in which only back gate is overlapped with drain region. This proposed structure of DG-TFET removes the trade-off between ambipolarity and HF performances by taking the merit of gate–drain overlap in terms of reduction in ambipolarity and suppressing its demerit with reduced gate–drain parasitic capacitance. Using 2-D simulation, it is observed that ambipolar conduction can be suppressed to a large extent in DG-TFET with only 20 nm of back gate–drain overlap, thus not limiting the scaling of drain region compared to symmetric gate–drain overlap DG-TFET (SGDO DG-TFET). Due to the presence of enhanced depletion layer in the drain region caused by a large vertical electrical field, tunneling width at drain–channel interface is found to be maximum in the proposed device, which eventually prevents the charge carriers to tunnel. Furthermore, ASGDO improves the HF performance parameters such as cutoff frequency and gain–bandwidth product compared to SGDO due to reduction in gate–drain parasitic capacitance, and this improvement is found to be consistent while scaling down the channel length.

Materials Today: Proceedings, Jul 1, 2023

ABSTRACT Carbon nanotube based FET devices are getting more and more importance today because of ... more ABSTRACT Carbon nanotube based FET devices are getting more and more importance today because of their high channel mobility and improved gate capacitance versus voltage characteristics. In this paper we compare and analyse the effect of gate capacitance on varying oxide thickness for silicon MOSTFET and CNTFET. It is seen that in nanometre regime quantum capacitance plays the major role in deciding the gate capacitance of a CNTFET and we find a favourable characteristics of decreasing gate capacitance with the decrease in the oxide thickness which is not possible to get in silicon MOSFET.

ABSTRACT In this paper we have analyzed the merits of CNTFET devices over MOSFET in nanoscale reg... more ABSTRACT In this paper we have analyzed the merits of CNTFET devices over MOSFET in nanoscale regime, by comparing the effect of oxide thickness on quantum capacitance. After this we have observed and analyzed the effect of variation of chiral vector and temperature on threshold voltage of CNTFET device. After simulation on HSPICE tool we can conclude that for high threshold voltage as required for low leakage in nanoscaled devices, chiral vector (m,n) should be relatively small. We have further analyzed the effect of temperature on threshold voltage in CNTFET devices and is found to be negligibly small. There is a little variation in the threshold voltage for both positive and negative temperatures.

Materials Science in Semiconductor Processing, Mar 1, 2015

Carbon nanotubes have some unique features and special properties that offer a great potential fo... more Carbon nanotubes have some unique features and special properties that offer a great potential for nano-electronic devices. In this paper, we have analyzed the effect of chiral vector, metal work function, channel length and High-K dielectric on threshold voltage of CNTFET devices. We have also compared the effect of oxide thickness on gate capacitance and justified the advantage of CNTFET over MOSFET in nanometer regime. Simulation on HSPICE tool shows that high threshold voltage can be achieved at low chiral vector in CNTFET. It is also observed that the temperature has a negligible effect on threshold voltage of CNTFET. After that we have simulated and observed the effect of channel length variation on threshold voltage of CNTFET as well as of MOSFET devices and given a theoretical analysis on it. We found an unusual, yet, favorable characteristics that the threshold voltage increases with decreasing channel length in CNTFET devices in deep nanometer regime especially when the gate length is around 10 nm; which is quite contrary to the well known short channel effects in MOSFET. It is observed that at or below 10 nm channel length the threshold voltage increases rapidly in case of CNTFET device whereas in case of MOSFET device the threshold voltage decreases drastically.

Elsevier eBooks, 2019

Abstract Metal oxide semiconductor field-effect transistor (MOSFET) is the main building block in... more Abstract Metal oxide semiconductor field-effect transistor (MOSFET) is the main building block in low-power and high-performance very large-scale integration (VLSI) chips for the last few decades. Device scaling is the guiding force toward technological advancements, which allows more devices to be integrated on a single die thereby allowing greater functionality per chip. The ultimate goal of scaling is to build an individual transistor that is smaller, faster, cheaper, and consuming low power. We see an exponential growth in device complexity in today's nanoscaled chip. However, device scaling to deep nanometer regime leads to exponential increase in leakage current and excessive heat generation. Moreover, process variability has caused a serious limitation to further scaling. It is believed that with a mix of chemistry, physics, and engineering, nanoelectronics may provide a solution to increasing fabrication costs and may allow integrated circuits to be scaled beyond the limits of the modern transistor. Carbon nanotube (CNT) and nanowire (NW)-based FETs (CNTFET and NWFET) have been analyzed and characterized in the laboratory and also been demonstrated as prototypes. This work first presents, a detailed explanation on chemical bonding and crystalline structures of these new devices and then an extensive simulation and analysis of CNTFET and NWFET devices and compared the results with conventional MOSFET and double gate MOSFET. From this study, it reveals that these new devices have got some excellent properties and favorable characteristics, which will definitely lead the future semiconductor devices in the post-silicon era.

In this paper we compare and justify the advantage of CNTFET devices over MOSFET devices in nanom... more In this paper we compare and justify the advantage of CNTFET devices over MOSFET devices in nanometer regime, by varying oxide thickness. Thereafter we have analyzed the effect of temperature in the characteristics of CNTFET devices. After simulation of Stanford nano-model-39 of CNTFET on HSPICE tool we observed that the effect of temperature on threshold voltage of CNTFET is negligibly small. Since there is little variation in threshold voltage so the leakage power due to temperature in scaled down scenario is very less compare to MOSFET devices.

Journal of Semiconductors, Nov 1, 2014

The exponential increase of leakage currents in a scaled device is an inevitable consequence of M... more The exponential increase of leakage currents in a scaled device is an inevitable consequence of MOSFET physics. Unfortunately constant field scaling reaches a performance limit. As the devices scaled down in nanometer regime the threshold voltage is also scaled, consequently the leakage power increases. If the channel length becomes too short, the depletion region from the drain can reach the source side and reduces the barrier for electron injection. In this paper we have analyzed the impact of channel length over threshold voltage of the CNTFET and MOSFET devices. With an analysis of HSPICE simulation results we found that the threshold voltage increases with decreasing channel length over a wide range of channel length in CNTFET that is not possible to get in MOSFET devices. The increase in threshold voltage in nanometer regime leads to reduce the leakage power and hence the CNTFET emerges as a power saving devices.