Senoj Joseph - Academia.edu (original) (raw)

Papers by Senoj Joseph

2021 7th International Conference on Advanced Computing and Communication Systems (ICACCS)

This paper is centered around a plan to develop a IOT based Smart baby cradle that would assist t... more This paper is centered around a plan to develop a IOT based Smart baby cradle that would assist the Parents with monitoring and keeping an eye on their infants regardless of whether they are at home or at work and can identify each activity of the infants from any inaccessible corner of the world. It is a brilliant, imaginative and defensive Cradle System to support a newborn child in a productive manner. This framework considers all the moment subtleties that are needed for the consideration and insurance of the Baby in the support. The plan of keenness and development accompanies the utilization of advancements which incorporate Internet of Things (IOT), Modules like Raspberry Pi, Gas sensor, sound sensor and Temperature sensor, Cry Detecting Mechanism, camera surveillance, and much more. To recognize each and every movement of Baby, various Sensors are connected to the Cradle: Gas & Temperature Sensing Module for discovery of wetness of the cradle. A Camera is fitted in the top Cradle for live video film & sound sensor to break down Cry Patterns. All the information which is being taken from the sensors will be put away in information base & recognized at normal stretches. Using all those data and images, parents can be sure about the safety and well being of their babies at any time in any given place.

2021 7th International Conference on Advanced Computing and Communication Systems (ICACCS), 2021

Water is the basic need of all living organisms and human mankind. In recent days the rapid popul... more Water is the basic need of all living organisms and human mankind. In recent days the rapid population growth has caused insufficiency and wastage of drinking water which has led to scarcity of water and uneven distribution of drinking water. The primary goal of this project is to check and maintain even distribution of water to all homes ensuring that there is no wastage and block in the supply of water and to generate the water bills to the individual households using IoT platforms. In order to implement this system, we will make use of Arduino. Water flow sensors and a valve to control the flow of water from the tank. Flow sensor generates a series of electric pulses through which water utilized by the user, flow rate and the amount of water supplied can be calculated. This project is proposed to solve issues by supplying water in a proper channelized manner using embedded technology and IoT platforms.

Programmable Device Circuits and Systems, 2011

A virtual hardware resource is provided by dynamically reconfigurable Field Programmable Gate Arr... more A virtual hardware resource is provided by dynamically reconfigurable Field Programmable Gate Array (FPGA) where the hardware circuits can be scheduled dynamically to the available resources. Significant performance and energy overheads are involved in reconfiguring an FPGA. The relationship between several hardware task scheduling algorithms and their impact on the amount of reconfigurations required to execute a set of hardware tasks is shown in this paper. By selectively locking the configurations within the reconfigurable tiles of an FPGA, the number of reconfigurations required can be reduced. Working area of the tiles can be improved and utilized for more number of tasks by assigning specific range of tiles for every task set.

Recent generations of FPGAs allow run-time partial reconfiguration. One of the challenging proble... more Recent generations of FPGAs allow run-time partial reconfiguration. One of the challenging problems in such a multitasking systems is online placement of task. Many online task placement algorithms designed for such partially reconfigurable systems have been proposed to provide efficient and fast task placement. In this paper two different approaches are being used to place the incoming tasks. The first method is uses a run-length based representation that defines the vacant slots on the FPGA. This compact representation allows the algorithm to locate a vacant area suitable to accommodate the incoming task quickly. In the proposed FPGA model, the CLBs are numbered according to Peano Space filling curve model. The second approach is based on harmonic packing. Simulation experiments indicate that proposed techniques result in low ratio of task rejection compared to existing techniques. Keywords-Partial Reconfiguration; Task Placement; Free Space Management; Peano Curve; FPGA; Bin packing __________________________________________________*****_________________________________________________

2021 7th International Conference on Advanced Computing and Communication Systems (ICACCS), 2021

An error could have occurred at the recipient end around a communication system once text is read... more An error could have occurred at the recipient end around a communication system once text is read from intermediate nodes. The Turbo Coder is used to get the originally transmitted data. Turbo code is an error - correcting code which now, when compared to some of the other error correction codes, has such a high error correction rate. The Turbo code is used in many different fields. NASA uses them for its communication with space. It has an encoder including a decoder. Two Recursive Convolutional Encoders and an Interleaver create the encoder. Two Soft in Soft out decoder, one Interleaver, one De-interleaver, and the MAP algorithm have been used to extract error-free data in the decoder. The MAP algorithm aims to reduce the number of iterations requisite to decode the relevant information. The encoder and decoder was configured individually through Modelsim, Verilog HDL (Xilinx), and Tanner.

International Journal of Engineering and Advanced Technology, 2020

In the field of digital signal and image processing the Fast Fourier Transform (FFT) is one of th... more In the field of digital signal and image processing the Fast Fourier Transform (FFT) is one of the rudimentary operations. Telecommunication, Automotive, Hearing devices, Voice recognition systems are some of the applications of Fast Fourier Transform. DFT is implemented using FFT which is a type of algorithm that computes DFT in a fast and efficient manner. This project concentrates on the development of the Fast Fourier Transform (FFT), based on Decimation In Time (DIT) domain, Radix2 algorithm, using VHDL as a design entity.The objective of this project is to establish an efficient design that computes FFT in a faster way. In this project FFT is implemented using modified booth multiplier and CLA and simulated on Xilinx ISE.

Wireless Personal Communications, 2018

The aggressive scaling of CMOS technology has inevitably led to vastly increased power dissipatio... more The aggressive scaling of CMOS technology has inevitably led to vastly increased power dissipation, process variability and reliability degradation, posing tremendous challenges to robust circuit design. To continue the success of integrated circuits, advanced design research must start in parallel with or even ahead of technology development. In this paper, an attempt is made to analyze various circuits' delay and power performance by introducing certain level of variation to important process parameters like threshold voltage (V th), mobility of carriers (l 0), oxide thickness (t ox) and doping concentration (n sd). Basic Monte Carlo simulation is carried out on these circuits to ascertain the stability in performances. A 16 9 1 multiplexer is considered for detailed analysis. SPICE characterization is done for three different input slew rates (0.1, 0.5 and 1 ns) against four different output load drive strengths (19, 29, 39 and 49 output capacitive load). From the obtained results, output slew rates and average power results are observed and discussed.

Sensors, 2021

The Industrial Internet of Things (IIoT) has led to the growth and expansion of various new oppor... more The Industrial Internet of Things (IIoT) has led to the growth and expansion of various new opportunities in the new Industrial Transformation. There have been notable challenges regarding the security of data and challenges related to privacy when collecting real-time and automatic data while observing applications in the industry. This paper proposes an Federated Transfer Learning for Authentication and Privacy Preservation Using Novel Supportive Twin Delayed DDPG (S-TD3) Algorithm for IIoT. In FT-Block (Federated transfer learning blockchain), several blockchains are applied to preserve privacy and security for all types of industrial applications. Additionally, by introducing the authentication mechanism based on transfer learning, blockchains can enhance the preservation and security standards for industrial applications. Specifically, Novel Supportive Twin Delayed DDPG trains the user model to authenticate specific regions. As it is considered one of the most open and scalable...

2019 International Conference on Intelligent Sustainable Systems (ICISS), 2019

With the growing population, Healthcare services and Monitoring of people are considered as the m... more With the growing population, Healthcare services and Monitoring of people are considered as the major needs in the recent years. There are many health monitoring systems which are either used for multi purpose or for a specific needs. On the other hand Assistive Technology (AT) is the one which would help the people to do their regular work without any manual support to meet their Activities of Daily Living (ADLs). The proposed system is a wearable device which could serve the purpose of health and motion monitoring along with an assistive technology. By the data from the accelerometer, microphone and sensors the activity of the person is determined. When there is any variation in the real time values from the default values an alert message will be sent to their close concern. On the other hand an alarm will be given on set time intervals for their regular activities like taking pills, insulin etc.

TENCON 2015 - 2015 IEEE Region 10 Conference, 2015

With the arrival of partial reconfiguration technology, modern FPGAs support tasks that can be lo... more With the arrival of partial reconfiguration technology, modern FPGAs support tasks that can be loaded in (removed from) the FPGA individually without interrupting other tasks already running on the same FPGA. Many online task placement algorithms designed for such partially reconfigurable systems have been proposed to provide efficient and fast task placement. A new approach for online placement of modules on reconfigurable devices, by managing the free space using a run-length based representation. This representation allows the algorithm to insert or delete tasks quickly and also to calculate the fragmentation easily. In the proposed FPGA model the CLBs are numbered according to Hilbert space filling curve model. The search algorithm will quickly identify a placement for the incoming task based on first fit mode or a fragmentation aware best Fit mode. Simulation experiments indicate that proposed techniques result in low ratio of task rejection and high FPGA utilization compared t...

Partially runtime reconfigurable FPGA’s allow hardware tasks to be placed and removed dynamically... more Partially runtime reconfigurable FPGA’s allow hardware tasks to be placed and removed dynamically at runtime. A fast and efficient algorithm for finding empty area is necessary for online placement algorithms. This paper deals with online scheduling and placement of tasks onto partially reconfigurable FPGAs in which CLB are labeled using Z-curve. The free space can be described easily using one dimensional run length based coding thereby making addition and deletion of task as simple as inserting entries into the run length list. Simulations indicate that the proposed methods produce better placement with 10% less task rejection when compared with related approaches Nowadays temperature distribution on the FPGA is a major issue. Hence the work is extended to develop a novel temperature aware model. This algorithm divides the entire surface of the FPGA into several clusters. Task are allocated to each cluster based on parameters like temperature, stress, fragmentation etc. The propos...

Placement is a key step in VLSI physical design cycle. With aggressive scaling if VLSI to Very De... more Placement is a key step in VLSI physical design cycle. With aggressive scaling if VLSI to Very Deep submicron level lead to higher power density which lead to generation on non uniform thermal map and hotspots. This scenario represent an important challenge in VLSI physical design to generate a layout that distribute temperature uniformly while optimizing traditional metrics like area, power and interconnect wire length. In this work a genetic algorithm based placement algorithm is proposed to that optimize temperature along with area and wire length.

International Journal of Computer Applications, 2014

Reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs), are very popular in today... more Reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs), are very popular in today's embedded systems design due to their low-cost, high-performance and flexibility. Partially Runtime-Reconfigurable (PRTR) FPGAs allow hardware tasks to be placed and removed dynamically at runtime. A novel 2D area fragmentation metric that takes into account feasibility of placement of future task arrivals is presented. Simulation experiments indicate that proposed technique yield better results than existing fragmentation estimation techniques when used in fragmentation aware placement.

Wireless Personal Communications, 2018

For field programmable gate arrays (FPGAs) to retain their semiconductor market and to be competi... more For field programmable gate arrays (FPGAs) to retain their semiconductor market and to be competitive as a choice for portable applications, the FPGA industry must adopt new techniques for dynamic and static power reduction. In this paper, a new scheme called 'self clock-gating' is introduced to reduce the dynamic power of basic logic elements. Circuits are designed using 16 nm Berkeley's Predictive technology model and tanner EDA tool is used for simulation. When we consider the average power, proposed architecture consumes 14% lesser than standard architecture. However, proposed architecture consumes only 6% of static power as that of standard architecture. If we consider the energy (power delay product), with the leakage reduction technique, the power delay product is 0.164 femto joules for the proposed architecture but in standard architecture, it is 0.200 femto joules.

2021 7th International Conference on Advanced Computing and Communication Systems (ICACCS)

This paper is centered around a plan to develop a IOT based Smart baby cradle that would assist t... more This paper is centered around a plan to develop a IOT based Smart baby cradle that would assist the Parents with monitoring and keeping an eye on their infants regardless of whether they are at home or at work and can identify each activity of the infants from any inaccessible corner of the world. It is a brilliant, imaginative and defensive Cradle System to support a newborn child in a productive manner. This framework considers all the moment subtleties that are needed for the consideration and insurance of the Baby in the support. The plan of keenness and development accompanies the utilization of advancements which incorporate Internet of Things (IOT), Modules like Raspberry Pi, Gas sensor, sound sensor and Temperature sensor, Cry Detecting Mechanism, camera surveillance, and much more. To recognize each and every movement of Baby, various Sensors are connected to the Cradle: Gas & Temperature Sensing Module for discovery of wetness of the cradle. A Camera is fitted in the top Cradle for live video film & sound sensor to break down Cry Patterns. All the information which is being taken from the sensors will be put away in information base & recognized at normal stretches. Using all those data and images, parents can be sure about the safety and well being of their babies at any time in any given place.

2021 7th International Conference on Advanced Computing and Communication Systems (ICACCS), 2021

Water is the basic need of all living organisms and human mankind. In recent days the rapid popul... more Water is the basic need of all living organisms and human mankind. In recent days the rapid population growth has caused insufficiency and wastage of drinking water which has led to scarcity of water and uneven distribution of drinking water. The primary goal of this project is to check and maintain even distribution of water to all homes ensuring that there is no wastage and block in the supply of water and to generate the water bills to the individual households using IoT platforms. In order to implement this system, we will make use of Arduino. Water flow sensors and a valve to control the flow of water from the tank. Flow sensor generates a series of electric pulses through which water utilized by the user, flow rate and the amount of water supplied can be calculated. This project is proposed to solve issues by supplying water in a proper channelized manner using embedded technology and IoT platforms.

Programmable Device Circuits and Systems, 2011

A virtual hardware resource is provided by dynamically reconfigurable Field Programmable Gate Arr... more A virtual hardware resource is provided by dynamically reconfigurable Field Programmable Gate Array (FPGA) where the hardware circuits can be scheduled dynamically to the available resources. Significant performance and energy overheads are involved in reconfiguring an FPGA. The relationship between several hardware task scheduling algorithms and their impact on the amount of reconfigurations required to execute a set of hardware tasks is shown in this paper. By selectively locking the configurations within the reconfigurable tiles of an FPGA, the number of reconfigurations required can be reduced. Working area of the tiles can be improved and utilized for more number of tasks by assigning specific range of tiles for every task set.

Recent generations of FPGAs allow run-time partial reconfiguration. One of the challenging proble... more Recent generations of FPGAs allow run-time partial reconfiguration. One of the challenging problems in such a multitasking systems is online placement of task. Many online task placement algorithms designed for such partially reconfigurable systems have been proposed to provide efficient and fast task placement. In this paper two different approaches are being used to place the incoming tasks. The first method is uses a run-length based representation that defines the vacant slots on the FPGA. This compact representation allows the algorithm to locate a vacant area suitable to accommodate the incoming task quickly. In the proposed FPGA model, the CLBs are numbered according to Peano Space filling curve model. The second approach is based on harmonic packing. Simulation experiments indicate that proposed techniques result in low ratio of task rejection compared to existing techniques. Keywords-Partial Reconfiguration; Task Placement; Free Space Management; Peano Curve; FPGA; Bin packing __________________________________________________*****_________________________________________________

2021 7th International Conference on Advanced Computing and Communication Systems (ICACCS), 2021

An error could have occurred at the recipient end around a communication system once text is read... more An error could have occurred at the recipient end around a communication system once text is read from intermediate nodes. The Turbo Coder is used to get the originally transmitted data. Turbo code is an error - correcting code which now, when compared to some of the other error correction codes, has such a high error correction rate. The Turbo code is used in many different fields. NASA uses them for its communication with space. It has an encoder including a decoder. Two Recursive Convolutional Encoders and an Interleaver create the encoder. Two Soft in Soft out decoder, one Interleaver, one De-interleaver, and the MAP algorithm have been used to extract error-free data in the decoder. The MAP algorithm aims to reduce the number of iterations requisite to decode the relevant information. The encoder and decoder was configured individually through Modelsim, Verilog HDL (Xilinx), and Tanner.

International Journal of Engineering and Advanced Technology, 2020

In the field of digital signal and image processing the Fast Fourier Transform (FFT) is one of th... more In the field of digital signal and image processing the Fast Fourier Transform (FFT) is one of the rudimentary operations. Telecommunication, Automotive, Hearing devices, Voice recognition systems are some of the applications of Fast Fourier Transform. DFT is implemented using FFT which is a type of algorithm that computes DFT in a fast and efficient manner. This project concentrates on the development of the Fast Fourier Transform (FFT), based on Decimation In Time (DIT) domain, Radix2 algorithm, using VHDL as a design entity.The objective of this project is to establish an efficient design that computes FFT in a faster way. In this project FFT is implemented using modified booth multiplier and CLA and simulated on Xilinx ISE.

Wireless Personal Communications, 2018

The aggressive scaling of CMOS technology has inevitably led to vastly increased power dissipatio... more The aggressive scaling of CMOS technology has inevitably led to vastly increased power dissipation, process variability and reliability degradation, posing tremendous challenges to robust circuit design. To continue the success of integrated circuits, advanced design research must start in parallel with or even ahead of technology development. In this paper, an attempt is made to analyze various circuits' delay and power performance by introducing certain level of variation to important process parameters like threshold voltage (V th), mobility of carriers (l 0), oxide thickness (t ox) and doping concentration (n sd). Basic Monte Carlo simulation is carried out on these circuits to ascertain the stability in performances. A 16 9 1 multiplexer is considered for detailed analysis. SPICE characterization is done for three different input slew rates (0.1, 0.5 and 1 ns) against four different output load drive strengths (19, 29, 39 and 49 output capacitive load). From the obtained results, output slew rates and average power results are observed and discussed.

Sensors, 2021

The Industrial Internet of Things (IIoT) has led to the growth and expansion of various new oppor... more The Industrial Internet of Things (IIoT) has led to the growth and expansion of various new opportunities in the new Industrial Transformation. There have been notable challenges regarding the security of data and challenges related to privacy when collecting real-time and automatic data while observing applications in the industry. This paper proposes an Federated Transfer Learning for Authentication and Privacy Preservation Using Novel Supportive Twin Delayed DDPG (S-TD3) Algorithm for IIoT. In FT-Block (Federated transfer learning blockchain), several blockchains are applied to preserve privacy and security for all types of industrial applications. Additionally, by introducing the authentication mechanism based on transfer learning, blockchains can enhance the preservation and security standards for industrial applications. Specifically, Novel Supportive Twin Delayed DDPG trains the user model to authenticate specific regions. As it is considered one of the most open and scalable...

2019 International Conference on Intelligent Sustainable Systems (ICISS), 2019

With the growing population, Healthcare services and Monitoring of people are considered as the m... more With the growing population, Healthcare services and Monitoring of people are considered as the major needs in the recent years. There are many health monitoring systems which are either used for multi purpose or for a specific needs. On the other hand Assistive Technology (AT) is the one which would help the people to do their regular work without any manual support to meet their Activities of Daily Living (ADLs). The proposed system is a wearable device which could serve the purpose of health and motion monitoring along with an assistive technology. By the data from the accelerometer, microphone and sensors the activity of the person is determined. When there is any variation in the real time values from the default values an alert message will be sent to their close concern. On the other hand an alarm will be given on set time intervals for their regular activities like taking pills, insulin etc.

TENCON 2015 - 2015 IEEE Region 10 Conference, 2015

With the arrival of partial reconfiguration technology, modern FPGAs support tasks that can be lo... more With the arrival of partial reconfiguration technology, modern FPGAs support tasks that can be loaded in (removed from) the FPGA individually without interrupting other tasks already running on the same FPGA. Many online task placement algorithms designed for such partially reconfigurable systems have been proposed to provide efficient and fast task placement. A new approach for online placement of modules on reconfigurable devices, by managing the free space using a run-length based representation. This representation allows the algorithm to insert or delete tasks quickly and also to calculate the fragmentation easily. In the proposed FPGA model the CLBs are numbered according to Hilbert space filling curve model. The search algorithm will quickly identify a placement for the incoming task based on first fit mode or a fragmentation aware best Fit mode. Simulation experiments indicate that proposed techniques result in low ratio of task rejection and high FPGA utilization compared t...

Partially runtime reconfigurable FPGA’s allow hardware tasks to be placed and removed dynamically... more Partially runtime reconfigurable FPGA’s allow hardware tasks to be placed and removed dynamically at runtime. A fast and efficient algorithm for finding empty area is necessary for online placement algorithms. This paper deals with online scheduling and placement of tasks onto partially reconfigurable FPGAs in which CLB are labeled using Z-curve. The free space can be described easily using one dimensional run length based coding thereby making addition and deletion of task as simple as inserting entries into the run length list. Simulations indicate that the proposed methods produce better placement with 10% less task rejection when compared with related approaches Nowadays temperature distribution on the FPGA is a major issue. Hence the work is extended to develop a novel temperature aware model. This algorithm divides the entire surface of the FPGA into several clusters. Task are allocated to each cluster based on parameters like temperature, stress, fragmentation etc. The propos...

Placement is a key step in VLSI physical design cycle. With aggressive scaling if VLSI to Very De... more Placement is a key step in VLSI physical design cycle. With aggressive scaling if VLSI to Very Deep submicron level lead to higher power density which lead to generation on non uniform thermal map and hotspots. This scenario represent an important challenge in VLSI physical design to generate a layout that distribute temperature uniformly while optimizing traditional metrics like area, power and interconnect wire length. In this work a genetic algorithm based placement algorithm is proposed to that optimize temperature along with area and wire length.

International Journal of Computer Applications, 2014

Reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs), are very popular in today... more Reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs), are very popular in today's embedded systems design due to their low-cost, high-performance and flexibility. Partially Runtime-Reconfigurable (PRTR) FPGAs allow hardware tasks to be placed and removed dynamically at runtime. A novel 2D area fragmentation metric that takes into account feasibility of placement of future task arrivals is presented. Simulation experiments indicate that proposed technique yield better results than existing fragmentation estimation techniques when used in fragmentation aware placement.

Wireless Personal Communications, 2018

For field programmable gate arrays (FPGAs) to retain their semiconductor market and to be competi... more For field programmable gate arrays (FPGAs) to retain their semiconductor market and to be competitive as a choice for portable applications, the FPGA industry must adopt new techniques for dynamic and static power reduction. In this paper, a new scheme called 'self clock-gating' is introduced to reduce the dynamic power of basic logic elements. Circuits are designed using 16 nm Berkeley's Predictive technology model and tanner EDA tool is used for simulation. When we consider the average power, proposed architecture consumes 14% lesser than standard architecture. However, proposed architecture consumes only 6% of static power as that of standard architecture. If we consider the energy (power delay product), with the leakage reduction technique, the power delay product is 0.164 femto joules for the proposed architecture but in standard architecture, it is 0.200 femto joules.