Abrar Siddique - Academia.edu (original) (raw)

Papers by Abrar Siddique

Research paper thumbnail of A Novel Optimized V-VLC Receiver Sensor Design Using μGA in Automotive Applications

Sensors

Vehicular visible light communication is known as a promising way of inter-vehicle communication.... more Vehicular visible light communication is known as a promising way of inter-vehicle communication. Vehicular VLC can ensure the significant advancement of safety and efficiency in traffic. It has disadvantages, such as unexpected glare on drivers in moving conditions, i.e., non-line-of-sight link at night. While designing a receiver, the most important factor is to ensure the optimal quality of the received signal. Within this context, to achieve an optimal communication quality, it is necessary to find the optimal maximum signal strength. Hereafter, a new receiver design is focused on in this paper at the circuit level, and a novel micro genetic algorithm is proposed to optimize the signal strength. The receiver can calculate the SNR, and it is possible to modify its structural design. The micro GA determines the alignment of the maximum signal strength at the receiver point rather than monitoring the signal strength for each angle. The results showed that the proposed scheme accura...

Research paper thumbnail of Novel multi-user MC-CSK modulation technique in visible light communication

Optical and Quantum Electronics

Research paper thumbnail of Linear/cubic measured pulse numerically with electrical jitter amplitude variations for the impact on fiber communication systems

Journal of Optical Communications

This study has simulated the raised cosine, linear, cubic measured pulses numerically with electr... more This study has simulated the raised cosine, linear, cubic measured pulses numerically with electrical jitter amplitude variations impact on fiber communication systems. The max Q factor, total electrical power variations against electrical jitter amplitude variations are demonstrated for various pulse configurations. The Q factor and signal power amplitude variations versus the time period with the spectral frequency are clarified based on various pulse configurations with an optimum amplitude jitter of 0.1 unit interval (UI). The total electrical power after the avalanche photodiode (APD) photodetector is measured numerically based on various pulse configurations with an optimum amplitude jitter of 0.1 UI.

Research paper thumbnail of Performance analysis of FIR based communication in multi user scenario using CSK

Optical and Quantum Electronics

Research paper thumbnail of Design and Analysis of a Novel 24 GHz Up-Conversion Mixer with Improved Derivative Super-Position Linearizer Technique for 5G Applications

Sensors

A 24 GHz high linear, high-gain up-conversion mixer is realized for fifth-generation (5G) applica... more A 24 GHz high linear, high-gain up-conversion mixer is realized for fifth-generation (5G) applications in the 65 nm CMOS process. The mixer’s linearity is increased by applying an Improved Derivative Super-Position (I-DS) technique cascaded between the mixer’s transconductance and switching stage. The high gain and stability of amplifiers in the transconductance stage of the mixer are achieved using novel tunable capacitive cross-coupled common source (TCC-CS) transistors. Using the I-DS, the third-order non-linear coefficient of current is closed to zero, enhancing the linearity. Additionally, a TCC-CS, which is realized by varactors, neutralizes the gate-to-drain parasitic capacitance (Cgd) of transistors in the transconductance stage of the mixer and contributes to the improvement of the gain and stability of the mixer. The measured 1 dB compression point OP1dB of the designed mixer is 4.1 dBm and IP1dB is 0.67 dBm at 24 GHz. The conversion gain of 4.1 dB at 24 GHz and 3.2 ± 0.9 ...

Research paper thumbnail of A CMOS Self-Calibrating Frequency Synthesizer

—A programmable phase-locked-loop (PLL)-based frequency synthesizer, capable of automatically adj... more —A programmable phase-locked-loop (PLL)-based frequency synthesizer, capable of automatically adjusting the nominal center frequency of the voltage-controlled oscillator (VCO) to an optimum value is described. In fully integrated PLLs, the VCO output frequency should be tunable over a wide range of frequencies, covering the desired range of the synthesizer output frequencies, for all processing variations and operating conditions. A wide tuning range realized by making the VCO gain large has the unwanted effect of increasing the phase noise at the output of the VCO, and hence the PLL as well. In this work, the wide tuning range is realized by digital control, with process variability managed through self-calibration. The PLL is only required to pull the oscillator output frequency to account for the digital quantization, temperature variations, and some margin. This allows the to be small, with better noise performance resulting. The prototype self-calibrating frequency synthesizer, capable of operating from 80 MHz to 1 GHz, demonstrates a measured absolute jitter of 20-ps rms at 480-MHz operating frequency. The prototype IC is fabricated in a 0.35-m 3-V digital CMOS process.

Research paper thumbnail of A Novel Optimized V-VLC Receiver Sensor Design Using μGA in Automotive Applications

Sensors

Vehicular visible light communication is known as a promising way of inter-vehicle communication.... more Vehicular visible light communication is known as a promising way of inter-vehicle communication. Vehicular VLC can ensure the significant advancement of safety and efficiency in traffic. It has disadvantages, such as unexpected glare on drivers in moving conditions, i.e., non-line-of-sight link at night. While designing a receiver, the most important factor is to ensure the optimal quality of the received signal. Within this context, to achieve an optimal communication quality, it is necessary to find the optimal maximum signal strength. Hereafter, a new receiver design is focused on in this paper at the circuit level, and a novel micro genetic algorithm is proposed to optimize the signal strength. The receiver can calculate the SNR, and it is possible to modify its structural design. The micro GA determines the alignment of the maximum signal strength at the receiver point rather than monitoring the signal strength for each angle. The results showed that the proposed scheme accura...

Research paper thumbnail of Novel multi-user MC-CSK modulation technique in visible light communication

Optical and Quantum Electronics

Research paper thumbnail of Linear/cubic measured pulse numerically with electrical jitter amplitude variations for the impact on fiber communication systems

Journal of Optical Communications

This study has simulated the raised cosine, linear, cubic measured pulses numerically with electr... more This study has simulated the raised cosine, linear, cubic measured pulses numerically with electrical jitter amplitude variations impact on fiber communication systems. The max Q factor, total electrical power variations against electrical jitter amplitude variations are demonstrated for various pulse configurations. The Q factor and signal power amplitude variations versus the time period with the spectral frequency are clarified based on various pulse configurations with an optimum amplitude jitter of 0.1 unit interval (UI). The total electrical power after the avalanche photodiode (APD) photodetector is measured numerically based on various pulse configurations with an optimum amplitude jitter of 0.1 UI.

Research paper thumbnail of Performance analysis of FIR based communication in multi user scenario using CSK

Optical and Quantum Electronics

Research paper thumbnail of Design and Analysis of a Novel 24 GHz Up-Conversion Mixer with Improved Derivative Super-Position Linearizer Technique for 5G Applications

Sensors

A 24 GHz high linear, high-gain up-conversion mixer is realized for fifth-generation (5G) applica... more A 24 GHz high linear, high-gain up-conversion mixer is realized for fifth-generation (5G) applications in the 65 nm CMOS process. The mixer’s linearity is increased by applying an Improved Derivative Super-Position (I-DS) technique cascaded between the mixer’s transconductance and switching stage. The high gain and stability of amplifiers in the transconductance stage of the mixer are achieved using novel tunable capacitive cross-coupled common source (TCC-CS) transistors. Using the I-DS, the third-order non-linear coefficient of current is closed to zero, enhancing the linearity. Additionally, a TCC-CS, which is realized by varactors, neutralizes the gate-to-drain parasitic capacitance (Cgd) of transistors in the transconductance stage of the mixer and contributes to the improvement of the gain and stability of the mixer. The measured 1 dB compression point OP1dB of the designed mixer is 4.1 dBm and IP1dB is 0.67 dBm at 24 GHz. The conversion gain of 4.1 dB at 24 GHz and 3.2 ± 0.9 ...

Research paper thumbnail of A CMOS Self-Calibrating Frequency Synthesizer

—A programmable phase-locked-loop (PLL)-based frequency synthesizer, capable of automatically adj... more —A programmable phase-locked-loop (PLL)-based frequency synthesizer, capable of automatically adjusting the nominal center frequency of the voltage-controlled oscillator (VCO) to an optimum value is described. In fully integrated PLLs, the VCO output frequency should be tunable over a wide range of frequencies, covering the desired range of the synthesizer output frequencies, for all processing variations and operating conditions. A wide tuning range realized by making the VCO gain large has the unwanted effect of increasing the phase noise at the output of the VCO, and hence the PLL as well. In this work, the wide tuning range is realized by digital control, with process variability managed through self-calibration. The PLL is only required to pull the oscillator output frequency to account for the digital quantization, temperature variations, and some margin. This allows the to be small, with better noise performance resulting. The prototype self-calibrating frequency synthesizer, capable of operating from 80 MHz to 1 GHz, demonstrates a measured absolute jitter of 20-ps rms at 480-MHz operating frequency. The prototype IC is fabricated in a 0.35-m 3-V digital CMOS process.