Rajnikant Soni - Academia.edu (original) (raw)

Papers by Rajnikant Soni

This paper is about two class-A voltage follower s like basic voltage follower and super source f... more This paper is about two class-A voltage follower s like basic voltage follower and super source foll ower. Both have their own advantages and limitations. Her e using ideal current source and then using a curre nt mirror as a source current analysis done for both basic voltage follower and super source follower. After doing th at process results are used to compare the performance of the above voltage followers. All analysis was supported by the simulation results. Various topologies of voltage f ollower like Basic voltage Follower, Super Source F ollower are designed in 180nm technology with ±1.8V power supply. These different The analysis are made in terms o f gain, bandwidth, offset and Delay using ELDO spice, IC station and Design architect of mentor graphics.

A method described in this paper is to design a Two Stage CMOS operational amplifier and analyze ... more A method described in this paper is to design a Two Stage CMOS operational amplifier and analyze the effect of various aspect ratios on the characteristics of this Op-Amp, which operates at 1.8V power supply using tsmc 0.18μm CMOS technology. In this paper trade-off curves are computed between all characteristics such as Gain, PM, GBW, ICMRR, CMRR, Slew Rate etc. The OPAMP designed is a two-stage CMOS OPAMP. The OPAMP is designed to exhibit a unity gain frequency of 14MHz and exhibits a gain of 59.98dB with a 61.235 phase margin. Design has been carried out in Mentor graphics tools. Simulation results are verified using Model Sim Eldo and Design Architect IC. The task of CMOS operational amplifiers (Op-Amps) design optimization is investigated in this work. This Paper focused on the optimization of various aspect ratios, which gave the result of different parameter. When this task is analyzed as a search problem, it can be translated into a multi-objective optimization application i...

An analytic design guide was formulated for the design of 3-stage CMOS OP amp with the nested Gm-... more An analytic design guide was formulated for the design of 3-stage CMOS OP amp with the nested Gm-C(NGCC) frequency compensation. The proposed design guide generates straight-forwardly the design parameters such as the W/L ratio and current of each transistor from the given design specifications, such as, gain-bandwidth, phase margin, the ratio of compensation capacitance to load capacitance. The applications of this design guide to the 10pF load capacitances, shows that the designed OP amp work with a reasonable performance in both cases, for the range of compensation capacitance from 10% to 100% of load capacitance. problem caused by the positive real zero, a series resistance to the miller capacitance is used in general for CMOS OP amps. The transfer function, stability, and phase margin conditions of multistage NMC amplifier are complicated to apply analytic design methodology. However, for multistage NGCC amplifier, a zero removal with feed-forward path is applied, which makes t...

International Journal of Advance Engineering and Research Development

An analytical design guide was formulation for the design of 3-stage CMOS Op-Amp with the Split-l... more An analytical design guide was formulation for the design of 3-stage CMOS Op-Amp with the Split-length Compensation. The proposed design guide generates straightforwardly the design parameters such as W/L ratio and current of each transistor fro m the given specification, such as, gain-bandwidth, phase margin, the ratio of compensation capacitance to load capacitance. The OPAMP is designed to exhibit a unity gain frequency of 1.25GHz and exhibits a gain of 79.87dB with an 89.68 phase margin. Design has been carried out in Mentor graphics tools.The results are compared with respect to standard characteristics of the op-amp with the help of graph and table. Simulation results agree with theoretical predictions. Simulations confirm that the settling time can be further improved by increasing the value of GBW; the settling time is achieved 49ns. It has been demonstrated that when W/L increases the parameters GBW increases and settling time reduces so the speed of Op-Amp is high.

IEEE Transactions on Electronic Computers, 1967

A simple waveform generator for display systems has been designed on the basis of homogeneous coo... more A simple waveform generator for display systems has been designed on the basis of homogeneous coordinate mathematics. This generator will draw points, lines, and general conic sections. The fundamental waveform used is the parabola. Circles, ellipses, and hyperbolas are merely perspective transformations of the basic parabola, which is represented by the parametric vector t= [t2, t, 1]. The design of the homogeneous conic generator is based upon the assumption that a multiplying digital-to-analog decoder can be built economically. The decoder produces an output voltage proportional to the product of a ten-bit digital number and a positive reference level; it must maintain 0.1 percent accuracy up to about 100 kHz. In its simplest form the generator would contain 11 decoders. Allowing subpicture scaling and centering requires 14; adding cubics requires 18; and the most complicated system, with three-dimensional cubics with a final perspective transformation as well as the two-dimensio...

In this paper we examine the need for high dynamic linearity in high speed digital-analog convert... more In this paper we examine the need for high dynamic linearity in high speed digital-analog converters for communications applications, and the challenges facing DAC designers attempting to maximize it. A brief discussion of a DAC designed for high dynamic linearity is then presented, followed by some predictions of future trends.

In this paper, a new voltage scaling type digital-analog converter (DAC) circuit using only diffe... more In this paper, a new voltage scaling type digital-analog converter (DAC) circuit using only differential difference current conveyors (DDCCs) is presented. The circuit does not employ any other active or passive elements. Only biasing currents of the active element are present, thus the proposed circuit has low power consumption.

DAC (digital-analog converter) is widely used in mixed-signal system and is also the typical inte... more DAC (digital-analog converter) is widely used in mixed-signal system and is also the typical integrated circuit device in semiconductor products. The statistical analysis on DAC papers and semiconductor market show that science and technology promote market rising prosperity and market demands expedite progress and innovation of scientific and technological. Now the research on DAC and the semiconductor market development in Asia-Pacific are gradually becoming more prominent, showing the globalization trend of semiconductor industry.

The required resolution of digital-analog-converter for optical OFDM was evaluated through simula... more The required resolution of digital-analog-converter for optical OFDM was evaluated through simulation and experiment. Signal degradation caused by quantization was independent of subcarrier modulation, and the performance improvement saturates with increasing bit resolution.

The most commonly used converter in digital-analog conversion is the one with an R/2R ladder circ... more The most commonly used converter in digital-analog conversion is the one with an R/2R ladder circuit. Accurate digital-analog converters (DAC) require extremely precise resistors. Although the trimming procedure is used to adjust the desired resistors' ratio, aging and environmental factors affect the accuracy and linearity of a converter, thus introducing random conversion errors and reducing the converter's applicability. With low

Circuits and Systems, 2004. …, 2004

In this paper, we describe implementations of binary-weighted and equal capacitance Floating Gate... more In this paper, we describe implementations of binary-weighted and equal capacitance Floating Gate Digital-Analog Converters (FGDACs). We im-prove the accuracy of charge amplifier DAC circuits and reduce their large element spread by utilizing epots in their implementations. ...

Circuits and Systems, 2005. …, 2005

Abstract—This paper describes an implementation of a com-pact and low-power 10-bit Floating-Gate ... more Abstract—This paper describes an implementation of a com-pact and low-power 10-bit Floating-Gate Digital-to-Analog Con-verter (FGDAC). Nonvolatile Floating-Gate voltage references are utilized to build a charge amplifier DAC architecture. This novel implementation ...

Solid-State Circuits, IEEE Journal of, Mar 1, 1996

A module generator (DSYN) creates optimized digital/analog converter (DAC) layouts given a set of... more A module generator (DSYN) creates optimized digital/analog converter (DAC) layouts given a set of specifications including performance constraints, a description of the implementation technology, and a set of design parameters. The generation process consists of a synthesis step followed by a layout step. During synthesis, a new constrained optimization method is coupled with combination of circuit simulation and DAC design equations. The layout step uses stretching and tiling operations on a set of primitive cells. ...

This paper is about two class-A voltage follower s like basic voltage follower and super source f... more This paper is about two class-A voltage follower s like basic voltage follower and super source foll ower. Both have their own advantages and limitations. Her e using ideal current source and then using a curre nt mirror as a source current analysis done for both basic voltage follower and super source follower. After doing th at process results are used to compare the performance of the above voltage followers. All analysis was supported by the simulation results. Various topologies of voltage f ollower like Basic voltage Follower, Super Source F ollower are designed in 180nm technology with ±1.8V power supply. These different The analysis are made in terms o f gain, bandwidth, offset and Delay using ELDO spice, IC station and Design architect of mentor graphics.

A method described in this paper is to design a Two Stage CMOS operational amplifier and analyze ... more A method described in this paper is to design a Two Stage CMOS operational amplifier and analyze the effect of various aspect ratios on the characteristics of this Op-Amp, which operates at 1.8V power supply using tsmc 0.18μm CMOS technology. In this paper trade-off curves are computed between all characteristics such as Gain, PM, GBW, ICMRR, CMRR, Slew Rate etc. The OPAMP designed is a two-stage CMOS OPAMP. The OPAMP is designed to exhibit a unity gain frequency of 14MHz and exhibits a gain of 59.98dB with a 61.235 phase margin. Design has been carried out in Mentor graphics tools. Simulation results are verified using Model Sim Eldo and Design Architect IC. The task of CMOS operational amplifiers (Op-Amps) design optimization is investigated in this work. This Paper focused on the optimization of various aspect ratios, which gave the result of different parameter. When this task is analyzed as a search problem, it can be translated into a multi-objective optimization application i...

An analytic design guide was formulated for the design of 3-stage CMOS OP amp with the nested Gm-... more An analytic design guide was formulated for the design of 3-stage CMOS OP amp with the nested Gm-C(NGCC) frequency compensation. The proposed design guide generates straight-forwardly the design parameters such as the W/L ratio and current of each transistor from the given design specifications, such as, gain-bandwidth, phase margin, the ratio of compensation capacitance to load capacitance. The applications of this design guide to the 10pF load capacitances, shows that the designed OP amp work with a reasonable performance in both cases, for the range of compensation capacitance from 10% to 100% of load capacitance. problem caused by the positive real zero, a series resistance to the miller capacitance is used in general for CMOS OP amps. The transfer function, stability, and phase margin conditions of multistage NMC amplifier are complicated to apply analytic design methodology. However, for multistage NGCC amplifier, a zero removal with feed-forward path is applied, which makes t...

International Journal of Advance Engineering and Research Development

An analytical design guide was formulation for the design of 3-stage CMOS Op-Amp with the Split-l... more An analytical design guide was formulation for the design of 3-stage CMOS Op-Amp with the Split-length Compensation. The proposed design guide generates straightforwardly the design parameters such as W/L ratio and current of each transistor fro m the given specification, such as, gain-bandwidth, phase margin, the ratio of compensation capacitance to load capacitance. The OPAMP is designed to exhibit a unity gain frequency of 1.25GHz and exhibits a gain of 79.87dB with an 89.68 phase margin. Design has been carried out in Mentor graphics tools.The results are compared with respect to standard characteristics of the op-amp with the help of graph and table. Simulation results agree with theoretical predictions. Simulations confirm that the settling time can be further improved by increasing the value of GBW; the settling time is achieved 49ns. It has been demonstrated that when W/L increases the parameters GBW increases and settling time reduces so the speed of Op-Amp is high.

IEEE Transactions on Electronic Computers, 1967

A simple waveform generator for display systems has been designed on the basis of homogeneous coo... more A simple waveform generator for display systems has been designed on the basis of homogeneous coordinate mathematics. This generator will draw points, lines, and general conic sections. The fundamental waveform used is the parabola. Circles, ellipses, and hyperbolas are merely perspective transformations of the basic parabola, which is represented by the parametric vector t= [t2, t, 1]. The design of the homogeneous conic generator is based upon the assumption that a multiplying digital-to-analog decoder can be built economically. The decoder produces an output voltage proportional to the product of a ten-bit digital number and a positive reference level; it must maintain 0.1 percent accuracy up to about 100 kHz. In its simplest form the generator would contain 11 decoders. Allowing subpicture scaling and centering requires 14; adding cubics requires 18; and the most complicated system, with three-dimensional cubics with a final perspective transformation as well as the two-dimensio...

In this paper we examine the need for high dynamic linearity in high speed digital-analog convert... more In this paper we examine the need for high dynamic linearity in high speed digital-analog converters for communications applications, and the challenges facing DAC designers attempting to maximize it. A brief discussion of a DAC designed for high dynamic linearity is then presented, followed by some predictions of future trends.

In this paper, a new voltage scaling type digital-analog converter (DAC) circuit using only diffe... more In this paper, a new voltage scaling type digital-analog converter (DAC) circuit using only differential difference current conveyors (DDCCs) is presented. The circuit does not employ any other active or passive elements. Only biasing currents of the active element are present, thus the proposed circuit has low power consumption.

DAC (digital-analog converter) is widely used in mixed-signal system and is also the typical inte... more DAC (digital-analog converter) is widely used in mixed-signal system and is also the typical integrated circuit device in semiconductor products. The statistical analysis on DAC papers and semiconductor market show that science and technology promote market rising prosperity and market demands expedite progress and innovation of scientific and technological. Now the research on DAC and the semiconductor market development in Asia-Pacific are gradually becoming more prominent, showing the globalization trend of semiconductor industry.

The required resolution of digital-analog-converter for optical OFDM was evaluated through simula... more The required resolution of digital-analog-converter for optical OFDM was evaluated through simulation and experiment. Signal degradation caused by quantization was independent of subcarrier modulation, and the performance improvement saturates with increasing bit resolution.

The most commonly used converter in digital-analog conversion is the one with an R/2R ladder circ... more The most commonly used converter in digital-analog conversion is the one with an R/2R ladder circuit. Accurate digital-analog converters (DAC) require extremely precise resistors. Although the trimming procedure is used to adjust the desired resistors' ratio, aging and environmental factors affect the accuracy and linearity of a converter, thus introducing random conversion errors and reducing the converter's applicability. With low

Circuits and Systems, 2004. …, 2004

In this paper, we describe implementations of binary-weighted and equal capacitance Floating Gate... more In this paper, we describe implementations of binary-weighted and equal capacitance Floating Gate Digital-Analog Converters (FGDACs). We im-prove the accuracy of charge amplifier DAC circuits and reduce their large element spread by utilizing epots in their implementations. ...

Circuits and Systems, 2005. …, 2005

Abstract—This paper describes an implementation of a com-pact and low-power 10-bit Floating-Gate ... more Abstract—This paper describes an implementation of a com-pact and low-power 10-bit Floating-Gate Digital-to-Analog Con-verter (FGDAC). Nonvolatile Floating-Gate voltage references are utilized to build a charge amplifier DAC architecture. This novel implementation ...

Solid-State Circuits, IEEE Journal of, Mar 1, 1996

A module generator (DSYN) creates optimized digital/analog converter (DAC) layouts given a set of... more A module generator (DSYN) creates optimized digital/analog converter (DAC) layouts given a set of specifications including performance constraints, a description of the implementation technology, and a set of design parameters. The generation process consists of a synthesis step followed by a layout step. During synthesis, a new constrained optimization method is coupled with combination of circuit simulation and DAC design equations. The layout step uses stretching and tiling operations on a set of primitive cells. ...