Sujit Patel - Academia.edu (original) (raw)
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Papers by Sujit Patel
IEEE Transactions on Circuits and Systems II: Express Briefs, 2000
In this paper, we made an analysis on the logic operations involved in conventional carry select ... more In this paper, we made an analysis on the logic operations involved in conventional carry select adder (CSLA) and CSLA based on binary to excess-1 converter (CSLA-BEC) to study the data-dependency, and to find redundant logic operations. We have eliminated all the redundant logic operations of conventional CSLA, and proposed a logic formulation for CSLA. In the proposed scheme, the carry-select operation is scheduled before the calculation of final-sum, which is different from the conventional approach. A CSLA based on the proposed scheme generate n-bit carry-words corresponding to input-carry '0' and '1', where n is the input bit-width. These carry words follow a specific bit-pattern which can be used for logic optimization of carry-select unit. Fixed input bits of carry generator unit also can be used for logic optimization. Based on this, an optimized design for carry-select unit and carry generator unit are obtained. Using these optimized logic units, an efficient design is obtained for CSLA. The proposed CSLA design involves significantly less area and delay than the recently proposed CSLA-BEC. Due to small carry-output delay, the proposed CSLA design is a good candidate for SQRT adder. We have derived architectures for SQRT-CSLA of bit-width 16, 32, and 64. Theoretical estimate shows that the proposed SQRT-CSLA involves nearly 16% less delay and 18% less area than the best of the existing SQRT-CSLA on average for different bit-widths. ASIC synthesis result shows that, best of the existing SQRT-CSLA design involves 44% more area-delay-product (ADP) and consumes 42% more energy than the proposed SQRT-CSLA on average for different bit-widths.
IEEE Transactions on Circuits and Systems II: Express Briefs, 2000
In this paper, we made an analysis on the logic operations involved in conventional carry select ... more In this paper, we made an analysis on the logic operations involved in conventional carry select adder (CSLA) and CSLA based on binary to excess-1 converter (CSLA-BEC) to study the data-dependency, and to find redundant logic operations. We have eliminated all the redundant logic operations of conventional CSLA, and proposed a logic formulation for CSLA. In the proposed scheme, the carry-select operation is scheduled before the calculation of final-sum, which is different from the conventional approach. A CSLA based on the proposed scheme generate n-bit carry-words corresponding to input-carry '0' and '1', where n is the input bit-width. These carry words follow a specific bit-pattern which can be used for logic optimization of carry-select unit. Fixed input bits of carry generator unit also can be used for logic optimization. Based on this, an optimized design for carry-select unit and carry generator unit are obtained. Using these optimized logic units, an efficient design is obtained for CSLA. The proposed CSLA design involves significantly less area and delay than the recently proposed CSLA-BEC. Due to small carry-output delay, the proposed CSLA design is a good candidate for SQRT adder. We have derived architectures for SQRT-CSLA of bit-width 16, 32, and 64. Theoretical estimate shows that the proposed SQRT-CSLA involves nearly 16% less delay and 18% less area than the best of the existing SQRT-CSLA on average for different bit-widths. ASIC synthesis result shows that, best of the existing SQRT-CSLA design involves 44% more area-delay-product (ADP) and consumes 42% more energy than the proposed SQRT-CSLA on average for different bit-widths.