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Papers by Sukanya Sagarika Meher

Research paper thumbnail of Parametric Approach for Routing Power Nets and Passive Transmission Lines as Part of Digital Cells

IEEE Transactions on Applied Superconductivity, 2019

In design and layout of rapid single flux quantum circuits, multiple independent biases are often... more In design and layout of rapid single flux quantum circuits, multiple independent biases are often desired to provide flexibility in timings of critical paths. In absence of automated power routing, power nets are often included as part of the layout cells. Multiple variants of each cell need to be manually created to support different biasing configurations. The parametric approach for routing power nets provides the flexibility to dynamically change biasing configurations, based on the same parametric cell. Multiple cells in a circuit block can be configured to be connected to a single power net or can be biased using several independent power nets. With the goal of minimizing the cell size, it is often difficult to maintain rotational symmetry for the power and passive transmission line (PTL) tracks. The parametric approach also enables rotating the cell while avoiding misalignment of the tracks. In addition, our implementation can dynamically add moat bridges to connect ground planes isolated by moats. This is especially useful to bridge very long moats that span two or more adjacent cells. Furthermore, this approach of dedicated tracks for power and PTL routing is also more amenable to design automation.

Research paper thumbnail of 64-GHz Operation of the Pseudorandom Binary Sequence Generator Using the Dual RSFQ/ERSFQ Standard Cell Library

IEEE Transactions on Applied Superconductivity

Research paper thumbnail of Observations in Use of a Tunnel Junction Model in Simulations of Josephson Digital Circuits

IEEE Transactions on Applied Superconductivity

Research paper thumbnail of Serial Biasing Technique for Electronic Design Automation in RSFQ Circuits

IEEE Transactions on Applied Superconductivity

Research paper thumbnail of Differential Propagation Delay Measurement of RSFQ Library Cells Using Ring Oscillators

IEEE Transactions on Applied Superconductivity

Performing comprehensive timing characterization of library cells and establishing their model-to... more Performing comprehensive timing characterization of library cells and establishing their model-to-hardware correlation are essential for building robust integrated circuits and scaling circuit complexity. To measure the propagation delay of fabricated library cells, we have designed a differential delay measurement scheme using SFQ ring oscillators. The reference and design-under-test (DUT) rings are designed using circuit elements that are either common to both rings or are of nominally similar design, except for the DUT. By inserting a single pulse in the ring, the oscillation period is measured using two methods: (1) direct voltage measurement, and (2) frequency measurement using a frequency divider followed by an SFQ-to-DC converter. Subtracting delay of the two rings gives us the propagation delay of the DUT. A 1 cm by 1 cm chip and another 5 mm by 5 mm chip, incorporating stand-alone ring oscillator test structures for different library cells, have been fabricated in the MIT-LL SFQ5ee process. The chips also contain test circuits to validate two variants of the input/output multiplexing scheme that facilitate reducing the pads requirement. Two copies of a chip with fifteen DUTs were tested. The measured and simulated results for the voltage and frequency of the ring are compared. The simulations account for critical current density (Jc) and sheet resistance (Rs) fabrication parameters. In addition, we have used the Jc as a single free parameter to get a better matching with measurement results. For one of the chips, a 15% higher Jc in simulations results in better matching with measured frequency results for all the DUTs. For example, the discrepancy between simulated and measured DUT ring frequency for the NOT cell was reduced from 19% to 1% when the Jc was changed from nominal to 15% higher in simulations. Detailed measurement and simulation results for several DUTs are presented.

Research paper thumbnail of Development of Superconductor Advanced Integrated Circuit Design Flow Using Synopsys Tools

IEEE Transactions on Applied Superconductivity, 2021

HYPRES developed an advanced design flow and design infrastructure for single-flux-quantum (SFQ) ... more HYPRES developed an advanced design flow and design infrastructure for single-flux-quantum (SFQ) superconductor integrated circuits using standard CMOS based EDA tools along with internally developed tools and has been successfully using this flow for the past several years. The design infrastructure includes the process design kit, advanced simulation methodology, and IC verification rule decks. The superconductor hierarchical circuit analyzer developed by HYPRES serves as bedrock of our simulation methodology facilitating circuit analysis and debugging including extraction of circuit parameter margins, analysis of Monte-Carlo simulations with process corners, as well as automated timing characterization. Using this proven design flow and infrastructure as a knowledge source, we have collaborated with Synopsys to enhance their tools for a full native tool enabled design flow and infrastructure, which represents a significant expansion in design capabilities and capacity for superconducting electronics. Using the 64-Bit arithmetic logic unit and a Pseudo Random Bit Sequence (PRBS) generator as reference circuits, we demonstrate the use of Synopsys tools for superconductor IC design including spice circuit simulations, plotting waveforms, margins analysis, Monte-Carlo simulations, HDL simulations with timing back-annotation, and IC validation including design rule checker and layout-versus-schematic checker.

Research paper thumbnail of Design of 64-Bit Arithmetic Logic Unit Using Improved Timing Characterization Methodology for RSFQ Cell Library

IEEE Transactions on Applied Superconductivity, 2021

Accurate timing characterization of library cells is essential for adopting the standard digital ... more Accurate timing characterization of library cells is essential for adopting the standard digital design flow using EDA tools, such as static timing analysis (STA) with timing back-annotation. For RSFQ circuits, the propagation delay of a cell is influenced by the input and output load. We have developed an automated timing characterization methodology that facilitates extraction of timing constraints and propagation delays for each cell as a function of all the possible permutations of input and output load. While being highly accurate, such a comprehensive timing characterization requires a large number of simulation runs. To significantly reduce the total number of simulation runs, we propose to analyze independently, rather than jointly, the effect of succeeding cells with standard preceding load and preceding cells with standard succeeding load. In addition, for succeeding cells with a storage loop, the delay of a cell is dependent on the state of the succeeding cell. STA tools cannot account for state-dependent timing variations. To mitigate state-dependent timing constraint violations, a state-dependent timing correction is added to the hold/set-up time. We have generated Liberty files for multiple process corners using the load dependent as well as standard load timing tables. We compare the timing accuracy for each methodology. We have designed and simulated a 64-bit ALU with 90,256 junctions with Verilog HDL and timing back-annotation across multiple process corners using Synopsys VCS tool. To validate the three timing characterization methodologies, we have evaluated their timing accuracies by comparing with full circuit simulations on representative ALU sub-blocks.

Research paper thumbnail of Green Power Generation in Mobile Phones and Laptops

International Journal of Computer Applications

With the increase in the use of portable devices in the present era, there arises a need to devel... more With the increase in the use of portable devices in the present era, there arises a need to develop greener and more efficient methods of generating energy to power these devices. Despite vacuum tube electronics’ weight and large associated battery, people living in the early 1900s have lugged such enormous “portable” radios to picnics and other events off the power grid. As electronics became smaller and required less power, batteries could grow smaller, enabling today’s wireless and mobile applications explosion. Portable devices (such as telephone, GPS, Walkman) are more and more popular and sophisticated. Thus they require more and more energy for comfortable use of new functionalities (TV on telephones, video on Walkman). The problem of the too frequent energy recharges of these objects, which make them less and less “nomadic”, is then a topical subject. Indeed, the interest of having the video-telephony on the mobile phone becomes very limited since it is necessary to recharge...

Research paper thumbnail of Dynamic spectral subtraction on AWGN speech

2015 2nd International Conference on Signal Processing and Integrated Networks (SPIN), 2015

ABSTRACT

Research paper thumbnail of Face recognition and facial expression identification using PCA

2014 IEEE International Advance Computing Conference (IACC), 2014

The face being the primary focus of attention in social interaction plays a major role in conveyi... more The face being the primary focus of attention in social interaction plays a major role in conveying identity and emotion. A facial recognition system is a computer application for automatically identifying or verifying a person from a digital image or a video frame from a video source. The main aim of this paper is to analyse the method of Principal Component Analysis (PCA) and its performance when applied to face recognition. This algorithm creates a subspace (face space) where the faces in a database are represented using a reduced number of features called feature vectors. The PCA technique has also been used to identify various facial expressions such as happy, sad, neutral, anger, disgust, fear etc. Experimental results that follow show that PCA based methods provide better face recognition with reasonably low error rates. From the paper, we conclude that PCA is a good technique for face recognition as it is able to identify faces fairly well with varying illuminations, facial expressions etc.

Research paper thumbnail of Superconductor Standard Cell Library for Advanced EDA Design

IEEE Transactions on Applied Superconductivity, 2021

Cell library is the keystone component that enables adoption of advanced electronic design automa... more Cell library is the keystone component that enables adoption of advanced electronic design automation (EDA) tools, such as logic synthesis and automatic place-and-route. The EDA tools are essential for scaling circuit complexity by orders of magnitude. We have designed a dual RSFQ/ERSFQ cell library for the MIT-LL SFQ5ee process, that can be used with the superconductor EDA tools suite that is being developed. In addition to satisfying the margins criterion, the performance of each cell has been optimized for Monte-Carlo statistical variations across multiple process corners including minimizing the spread of timing distributions. To enable a digital design flow using HDL simulations with timing back-annotation Liberty files have been developed for multiple process corners, using the load-dependent timing char-acterization. The cells have been designed for a standard height of 40 μm with a grid size of 20 μm. The library provides dedicated tracks for signal and power routing. Multiple independent biases are supported for RSFQ designs. The cells can be interconnected either by abutting or using passive transmission lines. Dedicated moat slots have been provided which are uniformly distributed across the cell. All cells are re-optimized post-layout. The library currently contains 22 unique types of cells. Initial validation of the cell library was performed by designing RSFQ and ERSFQ shift registers for the MIT-LL SFQ5ee fabrication process, which yielded wide operating margins. In addition, we present measurement results for a chip designed and fabricated to characterize several library cells using a multiplexing scheme.

Research paper thumbnail of Parametric Approach for Routing Power Nets and Passive Transmission Lines as Part of Digital Cells

IEEE Transactions on Applied Superconductivity, 2019

In design and layout of rapid single flux quantum circuits, multiple independent biases are often... more In design and layout of rapid single flux quantum circuits, multiple independent biases are often desired to provide flexibility in timings of critical paths. In absence of automated power routing, power nets are often included as part of the layout cells. Multiple variants of each cell need to be manually created to support different biasing configurations. The parametric approach for routing power nets provides the flexibility to dynamically change biasing configurations, based on the same parametric cell. Multiple cells in a circuit block can be configured to be connected to a single power net or can be biased using several independent power nets. With the goal of minimizing the cell size, it is often difficult to maintain rotational symmetry for the power and passive transmission line (PTL) tracks. The parametric approach also enables rotating the cell while avoiding misalignment of the tracks. In addition, our implementation can dynamically add moat bridges to connect ground planes isolated by moats. This is especially useful to bridge very long moats that span two or more adjacent cells. Furthermore, this approach of dedicated tracks for power and PTL routing is also more amenable to design automation.

Research paper thumbnail of 64-GHz Operation of the Pseudorandom Binary Sequence Generator Using the Dual RSFQ/ERSFQ Standard Cell Library

IEEE Transactions on Applied Superconductivity

Research paper thumbnail of Observations in Use of a Tunnel Junction Model in Simulations of Josephson Digital Circuits

IEEE Transactions on Applied Superconductivity

Research paper thumbnail of Serial Biasing Technique for Electronic Design Automation in RSFQ Circuits

IEEE Transactions on Applied Superconductivity

Research paper thumbnail of Differential Propagation Delay Measurement of RSFQ Library Cells Using Ring Oscillators

IEEE Transactions on Applied Superconductivity

Performing comprehensive timing characterization of library cells and establishing their model-to... more Performing comprehensive timing characterization of library cells and establishing their model-to-hardware correlation are essential for building robust integrated circuits and scaling circuit complexity. To measure the propagation delay of fabricated library cells, we have designed a differential delay measurement scheme using SFQ ring oscillators. The reference and design-under-test (DUT) rings are designed using circuit elements that are either common to both rings or are of nominally similar design, except for the DUT. By inserting a single pulse in the ring, the oscillation period is measured using two methods: (1) direct voltage measurement, and (2) frequency measurement using a frequency divider followed by an SFQ-to-DC converter. Subtracting delay of the two rings gives us the propagation delay of the DUT. A 1 cm by 1 cm chip and another 5 mm by 5 mm chip, incorporating stand-alone ring oscillator test structures for different library cells, have been fabricated in the MIT-LL SFQ5ee process. The chips also contain test circuits to validate two variants of the input/output multiplexing scheme that facilitate reducing the pads requirement. Two copies of a chip with fifteen DUTs were tested. The measured and simulated results for the voltage and frequency of the ring are compared. The simulations account for critical current density (Jc) and sheet resistance (Rs) fabrication parameters. In addition, we have used the Jc as a single free parameter to get a better matching with measurement results. For one of the chips, a 15% higher Jc in simulations results in better matching with measured frequency results for all the DUTs. For example, the discrepancy between simulated and measured DUT ring frequency for the NOT cell was reduced from 19% to 1% when the Jc was changed from nominal to 15% higher in simulations. Detailed measurement and simulation results for several DUTs are presented.

Research paper thumbnail of Development of Superconductor Advanced Integrated Circuit Design Flow Using Synopsys Tools

IEEE Transactions on Applied Superconductivity, 2021

HYPRES developed an advanced design flow and design infrastructure for single-flux-quantum (SFQ) ... more HYPRES developed an advanced design flow and design infrastructure for single-flux-quantum (SFQ) superconductor integrated circuits using standard CMOS based EDA tools along with internally developed tools and has been successfully using this flow for the past several years. The design infrastructure includes the process design kit, advanced simulation methodology, and IC verification rule decks. The superconductor hierarchical circuit analyzer developed by HYPRES serves as bedrock of our simulation methodology facilitating circuit analysis and debugging including extraction of circuit parameter margins, analysis of Monte-Carlo simulations with process corners, as well as automated timing characterization. Using this proven design flow and infrastructure as a knowledge source, we have collaborated with Synopsys to enhance their tools for a full native tool enabled design flow and infrastructure, which represents a significant expansion in design capabilities and capacity for superconducting electronics. Using the 64-Bit arithmetic logic unit and a Pseudo Random Bit Sequence (PRBS) generator as reference circuits, we demonstrate the use of Synopsys tools for superconductor IC design including spice circuit simulations, plotting waveforms, margins analysis, Monte-Carlo simulations, HDL simulations with timing back-annotation, and IC validation including design rule checker and layout-versus-schematic checker.

Research paper thumbnail of Design of 64-Bit Arithmetic Logic Unit Using Improved Timing Characterization Methodology for RSFQ Cell Library

IEEE Transactions on Applied Superconductivity, 2021

Accurate timing characterization of library cells is essential for adopting the standard digital ... more Accurate timing characterization of library cells is essential for adopting the standard digital design flow using EDA tools, such as static timing analysis (STA) with timing back-annotation. For RSFQ circuits, the propagation delay of a cell is influenced by the input and output load. We have developed an automated timing characterization methodology that facilitates extraction of timing constraints and propagation delays for each cell as a function of all the possible permutations of input and output load. While being highly accurate, such a comprehensive timing characterization requires a large number of simulation runs. To significantly reduce the total number of simulation runs, we propose to analyze independently, rather than jointly, the effect of succeeding cells with standard preceding load and preceding cells with standard succeeding load. In addition, for succeeding cells with a storage loop, the delay of a cell is dependent on the state of the succeeding cell. STA tools cannot account for state-dependent timing variations. To mitigate state-dependent timing constraint violations, a state-dependent timing correction is added to the hold/set-up time. We have generated Liberty files for multiple process corners using the load dependent as well as standard load timing tables. We compare the timing accuracy for each methodology. We have designed and simulated a 64-bit ALU with 90,256 junctions with Verilog HDL and timing back-annotation across multiple process corners using Synopsys VCS tool. To validate the three timing characterization methodologies, we have evaluated their timing accuracies by comparing with full circuit simulations on representative ALU sub-blocks.

Research paper thumbnail of Green Power Generation in Mobile Phones and Laptops

International Journal of Computer Applications

With the increase in the use of portable devices in the present era, there arises a need to devel... more With the increase in the use of portable devices in the present era, there arises a need to develop greener and more efficient methods of generating energy to power these devices. Despite vacuum tube electronics’ weight and large associated battery, people living in the early 1900s have lugged such enormous “portable” radios to picnics and other events off the power grid. As electronics became smaller and required less power, batteries could grow smaller, enabling today’s wireless and mobile applications explosion. Portable devices (such as telephone, GPS, Walkman) are more and more popular and sophisticated. Thus they require more and more energy for comfortable use of new functionalities (TV on telephones, video on Walkman). The problem of the too frequent energy recharges of these objects, which make them less and less “nomadic”, is then a topical subject. Indeed, the interest of having the video-telephony on the mobile phone becomes very limited since it is necessary to recharge...

Research paper thumbnail of Dynamic spectral subtraction on AWGN speech

2015 2nd International Conference on Signal Processing and Integrated Networks (SPIN), 2015

ABSTRACT

Research paper thumbnail of Face recognition and facial expression identification using PCA

2014 IEEE International Advance Computing Conference (IACC), 2014

The face being the primary focus of attention in social interaction plays a major role in conveyi... more The face being the primary focus of attention in social interaction plays a major role in conveying identity and emotion. A facial recognition system is a computer application for automatically identifying or verifying a person from a digital image or a video frame from a video source. The main aim of this paper is to analyse the method of Principal Component Analysis (PCA) and its performance when applied to face recognition. This algorithm creates a subspace (face space) where the faces in a database are represented using a reduced number of features called feature vectors. The PCA technique has also been used to identify various facial expressions such as happy, sad, neutral, anger, disgust, fear etc. Experimental results that follow show that PCA based methods provide better face recognition with reasonably low error rates. From the paper, we conclude that PCA is a good technique for face recognition as it is able to identify faces fairly well with varying illuminations, facial expressions etc.

Research paper thumbnail of Superconductor Standard Cell Library for Advanced EDA Design

IEEE Transactions on Applied Superconductivity, 2021

Cell library is the keystone component that enables adoption of advanced electronic design automa... more Cell library is the keystone component that enables adoption of advanced electronic design automation (EDA) tools, such as logic synthesis and automatic place-and-route. The EDA tools are essential for scaling circuit complexity by orders of magnitude. We have designed a dual RSFQ/ERSFQ cell library for the MIT-LL SFQ5ee process, that can be used with the superconductor EDA tools suite that is being developed. In addition to satisfying the margins criterion, the performance of each cell has been optimized for Monte-Carlo statistical variations across multiple process corners including minimizing the spread of timing distributions. To enable a digital design flow using HDL simulations with timing back-annotation Liberty files have been developed for multiple process corners, using the load-dependent timing char-acterization. The cells have been designed for a standard height of 40 μm with a grid size of 20 μm. The library provides dedicated tracks for signal and power routing. Multiple independent biases are supported for RSFQ designs. The cells can be interconnected either by abutting or using passive transmission lines. Dedicated moat slots have been provided which are uniformly distributed across the cell. All cells are re-optimized post-layout. The library currently contains 22 unique types of cells. Initial validation of the cell library was performed by designing RSFQ and ERSFQ shift registers for the MIT-LL SFQ5ee fabrication process, which yielded wide operating margins. In addition, we present measurement results for a chip designed and fabricated to characterize several library cells using a multiplexing scheme.