T. Georgantas - Academia.edu (original) (raw)

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Although attractive as a highly integrated solution, direct conversion architecture suffers from ... more Although attractive as a highly integrated solution, direct conversion architecture suffers from problems such as DC offsets, flicker noise and poor quadrature matching, that are further aggravated by using CMOS technology [1]. Furthermore, the 802.11a standard high bit-rate modes require closely matched I/Q frequency response. To alleviate those limitations, a transceiver topology allowing the use of the companion digital chip for calibration, has been implemented as shown in Fig. 20.2.1. Both transmitter and receiver use direct conversion and employ fully differential signal paths. By adding loop-back switches, the DC offset, TX and RX I/Q gain mismatch and I/Q frequency response can be independently calculated and corrected during the idle time between frames or at power-up.

A transceiver for transmitting and receiving signals includes a transmitter operative to up-conve... more A transceiver for transmitting and receiving signals includes a transmitter operative to up-convert baseband signals from a baseband frequency into RF signals at a radio frequency (RF) frequency and output the RF signals, a receiver operative to receive RF signals and down-convert the RF signals into baseband signals having the baseband frequency, and a plurality of calibration paths coupling the transmitter to the receiver. Any of the calibration paths can be selected to be active when calibrating components of the transceiver. Tunable components can use calibration information to optimize transceiver performance.

2014 IEEE Radio Frequency Integrated Circuits Symposium, 2014

ABSTRACT

2014 IEEE Radio Frequency Integrated Circuits Symposium, 2014

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC., 2003

... An integer-N PLL using a third-order passive loop filter generates the LO signal at half ... ... more ... An integer-N PLL using a third-order passive loop filter generates the LO signal at half ... The programmable divider in the feedback loop is formed by cascaded 2/3 dividers giving ... Gilbert cell-based doubler, and quad-rature signals are generated by second-order polyphase filters ...

ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705), 2003

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571), 2004

A single-chip 2.4 GHz, zero-IF transceiver for IEEE 802.11 b/g WLAN systems is fabricated on a 0.... more A single-chip 2.4 GHz, zero-IF transceiver for IEEE 802.11 b/g WLAN systems is fabricated on a 0.18 μm CMOS technology. Based on an innovative system architecture using digital calibration, analog circuit imperfections are eliminated. The transceiver features enhanced phase noise performance with the use of a fractional-N synthesizer. A switched configuration allows for the same filters to be used on

IEEE Journal of Solid-State Circuits, 2003

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC., 2003

... An integer-N PLL using a third-order passive loop filter generates the LO signal at half ... ... more ... An integer-N PLL using a third-order passive loop filter generates the LO signal at half ... The programmable divider in the feedback loop is formed by cascaded 2/3 dividers giving ... Gilbert cell-based doubler, and quad-rature signals are generated by second-order polyphase filters ...

Although attractive as a highly integrated solution, direct conversion architecture suffers from ... more Although attractive as a highly integrated solution, direct conversion architecture suffers from problems such as DC offsets, flicker noise and poor quadrature matching, that are further aggravated by using CMOS technology [1]. Furthermore, the 802.11a standard high bit-rate modes require closely matched I/Q frequency response. To alleviate those limitations, a transceiver topology allowing the use of the companion digital chip for calibration, has been implemented as shown in Fig. 20.2.1. Both transmitter and receiver use direct conversion and employ fully differential signal paths. By adding loop-back switches, the DC offset, TX and RX I/Q gain mismatch and I/Q frequency response can be independently calculated and corrected during the idle time between frames or at power-up.

A transceiver for transmitting and receiving signals includes a transmitter operative to up-conve... more A transceiver for transmitting and receiving signals includes a transmitter operative to up-convert baseband signals from a baseband frequency into RF signals at a radio frequency (RF) frequency and output the RF signals, a receiver operative to receive RF signals and down-convert the RF signals into baseband signals having the baseband frequency, and a plurality of calibration paths coupling the transmitter to the receiver. Any of the calibration paths can be selected to be active when calibrating components of the transceiver. Tunable components can use calibration information to optimize transceiver performance.

2014 IEEE Radio Frequency Integrated Circuits Symposium, 2014

ABSTRACT

2014 IEEE Radio Frequency Integrated Circuits Symposium, 2014

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC., 2003

... An integer-N PLL using a third-order passive loop filter generates the LO signal at half ... ... more ... An integer-N PLL using a third-order passive loop filter generates the LO signal at half ... The programmable divider in the feedback loop is formed by cascaded 2/3 dividers giving ... Gilbert cell-based doubler, and quad-rature signals are generated by second-order polyphase filters ...

ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705), 2003

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571), 2004

A single-chip 2.4 GHz, zero-IF transceiver for IEEE 802.11 b/g WLAN systems is fabricated on a 0.... more A single-chip 2.4 GHz, zero-IF transceiver for IEEE 802.11 b/g WLAN systems is fabricated on a 0.18 μm CMOS technology. Based on an innovative system architecture using digital calibration, analog circuit imperfections are eliminated. The transceiver features enhanced phase noise performance with the use of a fractional-N synthesizer. A switched configuration allows for the same filters to be used on

IEEE Journal of Solid-State Circuits, 2003

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC., 2003

... An integer-N PLL using a third-order passive loop filter generates the LO signal at half ... ... more ... An integer-N PLL using a third-order passive loop filter generates the LO signal at half ... The programmable divider in the feedback loop is formed by cascaded 2/3 dividers giving ... Gilbert cell-based doubler, and quad-rature signals are generated by second-order polyphase filters ...

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