Taewoo Kim - Academia.edu (original) (raw)

Papers by Taewoo Kim

Technical Digest - International Electron Devices Meeting, IEDM, 2009

We have fabricated 30 nm In 0.7 Ga 0.3 As Inverted-Type HEMTs with outstanding logic performance,... more We have fabricated 30 nm In 0.7 Ga 0.3 As Inverted-Type HEMTs with outstanding logic performance, scalability and high frequency characteristics. The motivation for this work is the demonstration of reduced gate leakage current in the Inverted HEMT structure. The fabricated devices show excellent L g scalability down to 30 nm. L g = 30 nm devices have been fabricated with exhibit g m = 1.27 mS/μm, S = 83 mV/dec, DIBL = 118 mV/V, I ON /I OFF = 4 x 10 4 , all at 0.5 V. More significantly, the removal of dopants from the barrier suppresses forward gate leakage current by over 100X when compared with equivalent normal HEMTs. The L g = 30 nm devices also feature record high-frequency characteristics for an inverted-type HEMT design with f T = 500 GHz and f max = 550 GHz.

Conference Proceedings - International Conference on Indium Phosphide and Related Materials, 2010

We have experimentally investigated the trade-offs involved in thinning down the channel of III-V... more We have experimentally investigated the trade-offs involved in thinning down the channel of III-V FETs with the ultimate goal of enhancing the electrostatic integrity and scalability of these devices. To do so, we have fabricated InAs HEMTs with a channel thickness of t ch = 5 nm and we have compared them against, InAs HEMTs with t ch = 10 nm. The fabricated thin-channel devices exhibit outstanding logic performance and scalability down to 40 nm in gate length. L g = 40 nm devices exhibit S = 72 mV/dec, DIBL = 72 mV/V, and I ON /I OFF = 2.5 x 10 4 , all at V DS = 0.5 V. However, there are trade-offs of using a thin channel which manifest themselves in a higher source resistance, lower transconductance, and lower f T when compared with InAs HEMTs with t ch = 10 nm.

Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena, 2011

Schottky diodes were fabricated on the InP/InAlAs heterostructures where the thickness of the InP... more Schottky diodes were fabricated on the InP/InAlAs heterostructures where the thickness of the InP ranges from 0 to 7 nm. A Ne-based atomic layer etching technique was utilized for precise control of the thickness of the InP layer. After removing the part of the InP layer, Pt/Ti/Pt/Au multilayer metallization was evaporated to form a Schottky contact. Thermal annealing was then carried out to drive Pt into the device layer. The electrical characteristics of the Schottky diodes were analyzed to determine the effect of a thin InP layer on the performance of the Schottky diodes. Transmission electron microscopy (TEM) was also utilized to investigate the diffusion of the metal into the semiconductor heterostructures. The experimental results show that the 7-nm-thick Pt can pass through the 4-nm-thick InP layer and reach the InAlAs layer. A Schottky junction was effectively formed within InAlAs layer when the thickness of the InP layer was equal or less than 4 nm for the 7-nm-thick Pt bot...

Applied Physics Express, 2012

We present a novel n-type InGaAs quantum-well metal-oxide-semiconductor field-effect transistor (... more We present a novel n-type InGaAs quantum-well metal-oxide-semiconductor field-effect transistor (QW-MOSFET) fabricated by a self-aligned gate-last process and investigate relevant Si-like manufacturing issues in future III-V MOSFETs. The device structure features a composite InP/ Al 2 O 3 gate barrier with a capacitance equivalent thickness (CET) of 3 nm and non alloyed Mo ohmic contacts. We have found that RIE introduces significant damage to the intrinsic device resulting in poor current drive and subthreshold swing. The effect is largely removed through a thermal annealing step. Thermally annealed QW-MOSFETs exhibit a subthreshold swing of 95 mV/dec, indicative of excellent interfacial characteristics. The peak mobility of the MOSFET is 2780 cm 2 V À1 s À1 .

Iprm 2011 23rd International Conference on Indium Phosphide and Related Materials, 2011

We have experimentally extracted the virtual-source electron injection velocity in InAs HEMTs wit... more We have experimentally extracted the virtual-source electron injection velocity in InAs HEMTs with a 5 nm thick channel. For long gate lengths, these devices exhibit noticeably worse injection velocity than thicker channel devices of a similar design. However, for very short gate lengths, as the devices approach the ballistic regime, the extracted injection velocity becomes rather independent of channel thickness. From these results, we can conclude that InAs-based QW-FETs with very thin channels have the potential of scaling to very short dimensions.

IEEE Electron Device Letters, 2007

The characteristics of 0.15-µm InAlAs/InGaAs pseudomorphic high-electron mobility transistors (p-... more The characteristics of 0.15-µm InAlAs/InGaAs pseudomorphic high-electron mobility transistors (p-HEMTs) that were fabricated using the Ne-based atomic layer etching (ALET) technology and the Ar-based conventional reactive ion etching (RIE) technology were investigated. As compared with the RIE, the ALET used a much lower plasma energy and thus produced much lower plasma-induced damages to the surface and bulk of the In 0.52 Al 0.48 As barrier and showed a much higher etch selectivity (∼70) of the InP spacer against the In 0.52 Al 0.48 As barrier. The 0.15-µm InAlAs/InGaAs p-HEMTs that were fabricated using the ALET exhibited improved G M,max (1.38 S/mm), I ON /I OFF (1.18 × 10 4), drain-induced barrier lowering (80 mV/V), threshold voltage uniformity (V th,avg = −190 mV and σ = 15 mV), and f T (233 GHz), mainly due to the extremely low plasma-induced damage in the Schottky gate area. Index Terms-Atomic layer etching (ALET), drain-induced barrier lowering (DIBL), I ON /I OFF ratio, pseudomorphic highelectron mobility transistor (p-HEMT), subthreshold slope.

IEEE Transactions on Electron Devices, 2008

We investigated 60-nm In 0.52 Al 0.48 As/ In 0.53 Ga 0.47 As pseudomorphic high-electron mobility... more We investigated 60-nm In 0.52 Al 0.48 As/ In 0.53 Ga 0.47 As pseudomorphic high-electron mobility transistors (p-HEMTs) fabricated by using a Ne-based atomic-layer-etching (ALET) technology. The ALET process produced a reproducible etch rate of 1.47 Å/cycle for an InP etch stop layer, an excellent InP etch selectivity of 70 against an In 0.52 Al 0.48 As barrier layer, and an rms surface-roughness value of 1.37 Å for the exposed In 0.52 Al 0.48 As barrier after removing the InP etch stop layer. The application of the ALET technology for the gate recess of 60-nm In 0.52 Al 0.48 As/In 0.53 Ga 0.47 As p-HEMTs produced improved device parameters, including transconductance (G M), cutoff frequencies (f T), and electron saturation velocity (υ sat) in the channel layer, which is mainly due to the high etch selectivity and low plasma-induced damage to the gate area. The 60-nm In 0.52 Al 0.48 As/In 0.53 Ga 0.47 As p-HEMTs fabricated by using the ALET technology exhibited G M,Max = 1.17 S/mm, f T = 398 GHz, and υ sat = 2.5 × 10 7 cm/s. Index Terms-Atomic-layer etching (ALET), channel electron saturation velocity (υ sat), gate-recess process, pseudomorphic high-electron mobility transistor (p-HEMT). I. INTRODUCTION T HE InP-BASED high-electron mobility transistors (HEMTs) have shown outstanding high-frequency performances. A short-circuited common-source current-gain cutoff frequency (f T) of 562 GHz for p-HEMTs, having a gate

The ability of Si CMOS to continue to scale down transistor size while delivering enhanced logic ... more The ability of Si CMOS to continue to scale down transistor size while delivering enhanced logic performance has recently come into question. An end to Moore's Law threatens to bring to a halt the microelectronics revolution: a historical 50 year run of exponential progress in the power of electronics that has profoundly transformed human society. The outstanding transport properties of certain III-V compound semiconductors make these materials attractive to address this problem. This paper outlines the case for III-V CMOS, harvests lessons from recent research on III-V High Electron Mobility Transistors (HEMTs) and summarizes some of the key challenges in front of a future III-V logic technology.

We have developed a new self-aligned gate technology for InGaAs High Electron Mobility Transistor... more We have developed a new self-aligned gate technology for InGaAs High Electron Mobility Transistors with non-alloyed Mo-based ohmic contacts and a very low parasitic capacitance gate design. The new process delivers a contact resistance of 7 Ohm-μm and a source resistance of 147 Ohm-μm. The nonalloyed Mo-based ohmic contacts show excellent thermal stability up to 600 °C. Using this technology, we have demonstrated a 60 nm gate length self-aligned InGaAs HEMT with g m = 2.1 mS/μm at V DS = 0.5 V, and f T = 580 GHz and f max = 675 GHz at V DS = 0.6 V. These are all record or near record values for this gate length.

In this paper, the lower-than-expected frequency performance observed in many AlGaN/GaN high elec... more In this paper, the lower-than-expected frequency performance observed in many AlGaN/GaN high electron mobility transistors (HEMTs) has been attributed to a significant drop of the intrinsic small-signal transconductance (gm) with respect to the intrinsic DC gm. To reduce this gm-collapse and improve high frequency performance, we have developed a new technology based on a combination of vertical gate-recess, oxygen plasma

Technical Digest - International Electron Devices Meeting, IEDM, 2009

We have fabricated 30 nm In 0.7 Ga 0.3 As Inverted-Type HEMTs with outstanding logic performance,... more We have fabricated 30 nm In 0.7 Ga 0.3 As Inverted-Type HEMTs with outstanding logic performance, scalability and high frequency characteristics. The motivation for this work is the demonstration of reduced gate leakage current in the Inverted HEMT structure. The fabricated devices show excellent L g scalability down to 30 nm. L g = 30 nm devices have been fabricated with exhibit g m = 1.27 mS/μm, S = 83 mV/dec, DIBL = 118 mV/V, I ON /I OFF = 4 x 10 4 , all at 0.5 V. More significantly, the removal of dopants from the barrier suppresses forward gate leakage current by over 100X when compared with equivalent normal HEMTs. The L g = 30 nm devices also feature record high-frequency characteristics for an inverted-type HEMT design with f T = 500 GHz and f max = 550 GHz.

Conference Proceedings - International Conference on Indium Phosphide and Related Materials, 2010

We have experimentally investigated the trade-offs involved in thinning down the channel of III-V... more We have experimentally investigated the trade-offs involved in thinning down the channel of III-V FETs with the ultimate goal of enhancing the electrostatic integrity and scalability of these devices. To do so, we have fabricated InAs HEMTs with a channel thickness of t ch = 5 nm and we have compared them against, InAs HEMTs with t ch = 10 nm. The fabricated thin-channel devices exhibit outstanding logic performance and scalability down to 40 nm in gate length. L g = 40 nm devices exhibit S = 72 mV/dec, DIBL = 72 mV/V, and I ON /I OFF = 2.5 x 10 4 , all at V DS = 0.5 V. However, there are trade-offs of using a thin channel which manifest themselves in a higher source resistance, lower transconductance, and lower f T when compared with InAs HEMTs with t ch = 10 nm.

Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena, 2011

Schottky diodes were fabricated on the InP/InAlAs heterostructures where the thickness of the InP... more Schottky diodes were fabricated on the InP/InAlAs heterostructures where the thickness of the InP ranges from 0 to 7 nm. A Ne-based atomic layer etching technique was utilized for precise control of the thickness of the InP layer. After removing the part of the InP layer, Pt/Ti/Pt/Au multilayer metallization was evaporated to form a Schottky contact. Thermal annealing was then carried out to drive Pt into the device layer. The electrical characteristics of the Schottky diodes were analyzed to determine the effect of a thin InP layer on the performance of the Schottky diodes. Transmission electron microscopy (TEM) was also utilized to investigate the diffusion of the metal into the semiconductor heterostructures. The experimental results show that the 7-nm-thick Pt can pass through the 4-nm-thick InP layer and reach the InAlAs layer. A Schottky junction was effectively formed within InAlAs layer when the thickness of the InP layer was equal or less than 4 nm for the 7-nm-thick Pt bot...

Applied Physics Express, 2012

We present a novel n-type InGaAs quantum-well metal-oxide-semiconductor field-effect transistor (... more We present a novel n-type InGaAs quantum-well metal-oxide-semiconductor field-effect transistor (QW-MOSFET) fabricated by a self-aligned gate-last process and investigate relevant Si-like manufacturing issues in future III-V MOSFETs. The device structure features a composite InP/ Al 2 O 3 gate barrier with a capacitance equivalent thickness (CET) of 3 nm and non alloyed Mo ohmic contacts. We have found that RIE introduces significant damage to the intrinsic device resulting in poor current drive and subthreshold swing. The effect is largely removed through a thermal annealing step. Thermally annealed QW-MOSFETs exhibit a subthreshold swing of 95 mV/dec, indicative of excellent interfacial characteristics. The peak mobility of the MOSFET is 2780 cm 2 V À1 s À1 .

Iprm 2011 23rd International Conference on Indium Phosphide and Related Materials, 2011

We have experimentally extracted the virtual-source electron injection velocity in InAs HEMTs wit... more We have experimentally extracted the virtual-source electron injection velocity in InAs HEMTs with a 5 nm thick channel. For long gate lengths, these devices exhibit noticeably worse injection velocity than thicker channel devices of a similar design. However, for very short gate lengths, as the devices approach the ballistic regime, the extracted injection velocity becomes rather independent of channel thickness. From these results, we can conclude that InAs-based QW-FETs with very thin channels have the potential of scaling to very short dimensions.

IEEE Electron Device Letters, 2007

The characteristics of 0.15-µm InAlAs/InGaAs pseudomorphic high-electron mobility transistors (p-... more The characteristics of 0.15-µm InAlAs/InGaAs pseudomorphic high-electron mobility transistors (p-HEMTs) that were fabricated using the Ne-based atomic layer etching (ALET) technology and the Ar-based conventional reactive ion etching (RIE) technology were investigated. As compared with the RIE, the ALET used a much lower plasma energy and thus produced much lower plasma-induced damages to the surface and bulk of the In 0.52 Al 0.48 As barrier and showed a much higher etch selectivity (∼70) of the InP spacer against the In 0.52 Al 0.48 As barrier. The 0.15-µm InAlAs/InGaAs p-HEMTs that were fabricated using the ALET exhibited improved G M,max (1.38 S/mm), I ON /I OFF (1.18 × 10 4), drain-induced barrier lowering (80 mV/V), threshold voltage uniformity (V th,avg = −190 mV and σ = 15 mV), and f T (233 GHz), mainly due to the extremely low plasma-induced damage in the Schottky gate area. Index Terms-Atomic layer etching (ALET), drain-induced barrier lowering (DIBL), I ON /I OFF ratio, pseudomorphic highelectron mobility transistor (p-HEMT), subthreshold slope.

IEEE Transactions on Electron Devices, 2008

We investigated 60-nm In 0.52 Al 0.48 As/ In 0.53 Ga 0.47 As pseudomorphic high-electron mobility... more We investigated 60-nm In 0.52 Al 0.48 As/ In 0.53 Ga 0.47 As pseudomorphic high-electron mobility transistors (p-HEMTs) fabricated by using a Ne-based atomic-layer-etching (ALET) technology. The ALET process produced a reproducible etch rate of 1.47 Å/cycle for an InP etch stop layer, an excellent InP etch selectivity of 70 against an In 0.52 Al 0.48 As barrier layer, and an rms surface-roughness value of 1.37 Å for the exposed In 0.52 Al 0.48 As barrier after removing the InP etch stop layer. The application of the ALET technology for the gate recess of 60-nm In 0.52 Al 0.48 As/In 0.53 Ga 0.47 As p-HEMTs produced improved device parameters, including transconductance (G M), cutoff frequencies (f T), and electron saturation velocity (υ sat) in the channel layer, which is mainly due to the high etch selectivity and low plasma-induced damage to the gate area. The 60-nm In 0.52 Al 0.48 As/In 0.53 Ga 0.47 As p-HEMTs fabricated by using the ALET technology exhibited G M,Max = 1.17 S/mm, f T = 398 GHz, and υ sat = 2.5 × 10 7 cm/s. Index Terms-Atomic-layer etching (ALET), channel electron saturation velocity (υ sat), gate-recess process, pseudomorphic high-electron mobility transistor (p-HEMT). I. INTRODUCTION T HE InP-BASED high-electron mobility transistors (HEMTs) have shown outstanding high-frequency performances. A short-circuited common-source current-gain cutoff frequency (f T) of 562 GHz for p-HEMTs, having a gate

The ability of Si CMOS to continue to scale down transistor size while delivering enhanced logic ... more The ability of Si CMOS to continue to scale down transistor size while delivering enhanced logic performance has recently come into question. An end to Moore's Law threatens to bring to a halt the microelectronics revolution: a historical 50 year run of exponential progress in the power of electronics that has profoundly transformed human society. The outstanding transport properties of certain III-V compound semiconductors make these materials attractive to address this problem. This paper outlines the case for III-V CMOS, harvests lessons from recent research on III-V High Electron Mobility Transistors (HEMTs) and summarizes some of the key challenges in front of a future III-V logic technology.

We have developed a new self-aligned gate technology for InGaAs High Electron Mobility Transistor... more We have developed a new self-aligned gate technology for InGaAs High Electron Mobility Transistors with non-alloyed Mo-based ohmic contacts and a very low parasitic capacitance gate design. The new process delivers a contact resistance of 7 Ohm-μm and a source resistance of 147 Ohm-μm. The nonalloyed Mo-based ohmic contacts show excellent thermal stability up to 600 °C. Using this technology, we have demonstrated a 60 nm gate length self-aligned InGaAs HEMT with g m = 2.1 mS/μm at V DS = 0.5 V, and f T = 580 GHz and f max = 675 GHz at V DS = 0.6 V. These are all record or near record values for this gate length.

In this paper, the lower-than-expected frequency performance observed in many AlGaN/GaN high elec... more In this paper, the lower-than-expected frequency performance observed in many AlGaN/GaN high electron mobility transistors (HEMTs) has been attributed to a significant drop of the intrinsic small-signal transconductance (gm) with respect to the intrinsic DC gm. To reduce this gm-collapse and improve high frequency performance, we have developed a new technology based on a combination of vertical gate-recess, oxygen plasma