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Papers by Christoforos Theodorou

Research paper thumbnail of Dynamic Variation In Nano-Scale Cmos Sram Cells Due To Lf/Rts Noise And Threshold Voltage

The dynamic variation in memory devices such as the Static Random Access Memory can give errors i... more The dynamic variation in memory devices such as the Static Random Access Memory can give errors in read or write operations. In this paper, the effect of low-frequency and random telegraph noise on the dynamic variation of one SRAM cell is detailed. The effect on circuit noise, speed, and length of time of processing is examined, using the Supply Read Retention Voltage and the Read Static Noise Margin. New test run methods are also developed. The obtained results simulation shows the importance of noise caused by dynamic variation, and the impact of Random Telegraph noise on SRAM variability is examined by evaluating the statistical distributions of Random Telegraph noise amplitude in the pull-up, pull-down. The threshold voltage mismatch between neighboring cell transistors due to intrinsic fluctuations typically contributes to larger reductions in static noise margin. Also the contribution of each of the SRAM transistor to total dynamic variation has been identified.

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Research paper thumbnail of Full front and back gate voltage range method for the parameter extraction of advanced FDSOI CMOS devices

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Research paper thumbnail of Dynamic variability in 14nm FD-SOI MOSFETs and transient simulation methodology

Solid-State Electronics, 2015

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Research paper thumbnail of Low frequency noise statistical characterization of 14nm FDSOI technology node

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Research paper thumbnail of Impact of Source–Drain Series Resistance on Drain Current Mismatch in Advanced Fully Depleted SOI n-MOSFETs

IEEE Electron Device Letters

In this letter, we demonstrate the existence of the source–drain series resistance mismatch and i... more In this letter, we demonstrate the existence of the source–drain series resistance mismatch and its impact on drain current variability with regard to the other mismatch parameters. To this end, we propose a new methodology for the drain current mismatch study based on YYY -function, enabling a precise determination of the various variability sources in advanced fully depleted silicon on insulator (SOI) MOS devices.

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Research paper thumbnail of Full gate voltage range Lambert-function based methodology for FDSOI MOSFET parameter extraction

A new full gate voltage range methodology using a Lambert W function based inversion charge model... more A new full gate voltage range methodology using a Lambert W function based inversion charge model, for extracting the electrical parameters in FDSOI nano-MOSFET devices, has been developed. Split capacitance–voltage measurements carried out on 14 nm technology FDSOI devices show that the inversion charge variation with gate voltage can be well described by a Lambert W function. Based on the drain current equation in the linear region including the inversion charge described by the Lambert function of gate voltage and the standard mobility equation enables five electrical MOSFET parameters to be extracted from experimental Id–Vg measurements (ideality factor, threshold voltage, low field mobility, first and second order mobility attenuation factors). The extracted parameters were compared with those extracted by the well-known Y-function in strong inversion region. The present methodology for extracting the electrical MOSFET parameters was verified over a wide range of channel length...

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Research paper thumbnail of New LFN and RTN analysis methodology in 28 and 14nm FD-SOI MOSFETs

2015 IEEE International Reliability Physics Symposium, 2015

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Research paper thumbnail of Drain-Current Flicker Noise Modeling in nMOSFETs From a 14-nm FDSOI Technology

IEEE Transactions on Electron Devices, 2015

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Research paper thumbnail of Impact of low-frequency noise variability on statistical parameter extraction in ultra-scaled CMOS devices

Electronics Letters

The impact on the extracted low-frequency noise (LFN) parameter values due to LFN variability in ... more The impact on the extracted low-frequency noise (LFN) parameter values due to LFN variability in CMOS devices is investigated. First, it is demonstrated that the noise level dispersion follows a log normal statistical distribution. Then, based on this feature, it is explained why the mean values from the linear data are different from the mean values (or median values) calculated from the log noise data. Finally, the consequence of this finding in terms of LFN characterisation issues and Monte Carlo LFN variability circuit simulation is discussed.

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Research paper thumbnail of Impact of front-back gate coupling on low frequency noise in 28 nm FDSOI MOSFETs

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2012

ABSTRACT Low-frequency (LF) noise has been studied on 28 nm FDSOI devices with ultra-thin silicon... more ABSTRACT Low-frequency (LF) noise has been studied on 28 nm FDSOI devices with ultra-thin silicon film (7 nm) and thin buried oxide (25 nm). A strong dependence of the noise level on the combination of the front and back biasing voltages was observed, and justified by the coupling effect of both Si/High-K dielectric and Si/SiO2 interface noise sources (channel/front oxide and channel/buried oxide), combined with the change of the Remote Coulomb scattering. From comparisons of the experimental and simulation results, it is shown that the main reason of this dependence is the distance of the charge distribution centroid from the interfaces, which is controlled by both front and back-gate bias voltages, and the way this distance affects the Remote Coulomb scattering coefficient a. A new LF noise model approach is proposed to include all these effects. This also allows us to assess the oxide trap density values for both interfaces.

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Research paper thumbnail of A new linear voltage-to-current converter with threshold voltage compensation for analog circuits applications in polycrystalline silicon TFT process

A new linear voltage-to-current (V-I) converter with threshold voltage compensation for analog ci... more A new linear voltage-to-current (V-I) converter with threshold voltage compensation for analog circuits design implemented with low-temperature polycrystalline silicon thin-film transistors (LT poly-Si TFTs) is proposed. The proposed V-I converter has been verified through simulations with Synopsys HSpice using level 62 RPI model. In order to obtain realistic simulations, parameters extraction in fabricated LT poly-Si TFTs was made. The proposed

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Research paper thumbnail of Low-frequency noise behavior of n-channel UTBB FD-SOI MOSFETs

2013 22nd International Conference on Noise and Fluctuations (ICNF), 2013

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Research paper thumbnail of Short Channel Effects on LTPS TFT Degradation

Journal of Display Technology, 2013

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Research paper thumbnail of Evolution of low frequency noise and noise variability through CMOS bulk technology nodes from 0.5μm down to 20nm

Solid-State Electronics, 2014

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Research paper thumbnail of Origin of the low-frequency noise in n-channel FinFETs

Solid-State Electronics, 2013

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Research paper thumbnail of Symmetrical unified compact model of short-channel double-gate MOSFETs

Solid-State Electronics, 2012

ABSTRACT An explicit charge-based unified compact drain current model for lightly doped or undope... more ABSTRACT An explicit charge-based unified compact drain current model for lightly doped or undoped DG MOSFETs is proposed. It takes into account the short-channel effects, the subthreshold slope degradation, the drain-induced barrier lowering and the channel length modulation effects. The model is valid and continuous in all regimes of operation and it has been validated by developing a Verilog-A code and comparing the model results of transfer and output characteristics with simulation results exhibiting an average error of about 3%. The efficient solution of the Lambert W function for the inversion charge and the symmetry of the model make it suitable for circuit simulation and allow fast and accurate simulations of the transistor characteristics.

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Research paper thumbnail of Analytical low-frequency noise model in the linear region of lightly doped nanoscale double-gate metal-oxide-semiconductor field-effect transistors

Journal of Applied Physics, 2010

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Research paper thumbnail of Low-Frequency Noise Sources in Advanced UTBB FD-SOI MOSFETs

IEEE Transactions on Electron Devices, 2000

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Research paper thumbnail of Analytical Modeling of Threshold Voltage and Interface Ideality Factor of Nanoscale Ultrathin Body and Buried Oxide SOI MOSFETs With Back Gate Control

IEEE Transactions on Electron Devices, 2000

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Research paper thumbnail of Origin of Low-Frequency Noise in the Low Drain Current Range of Bottom-Gate Amorphous IGZO Thin-Film Transistors

IEEE Electron Device Letters, 2000

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Research paper thumbnail of Dynamic Variation In Nano-Scale Cmos Sram Cells Due To Lf/Rts Noise And Threshold Voltage

The dynamic variation in memory devices such as the Static Random Access Memory can give errors i... more The dynamic variation in memory devices such as the Static Random Access Memory can give errors in read or write operations. In this paper, the effect of low-frequency and random telegraph noise on the dynamic variation of one SRAM cell is detailed. The effect on circuit noise, speed, and length of time of processing is examined, using the Supply Read Retention Voltage and the Read Static Noise Margin. New test run methods are also developed. The obtained results simulation shows the importance of noise caused by dynamic variation, and the impact of Random Telegraph noise on SRAM variability is examined by evaluating the statistical distributions of Random Telegraph noise amplitude in the pull-up, pull-down. The threshold voltage mismatch between neighboring cell transistors due to intrinsic fluctuations typically contributes to larger reductions in static noise margin. Also the contribution of each of the SRAM transistor to total dynamic variation has been identified.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Full front and back gate voltage range method for the parameter extraction of advanced FDSOI CMOS devices

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Dynamic variability in 14nm FD-SOI MOSFETs and transient simulation methodology

Solid-State Electronics, 2015

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Research paper thumbnail of Low frequency noise statistical characterization of 14nm FDSOI technology node

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Research paper thumbnail of Impact of Source–Drain Series Resistance on Drain Current Mismatch in Advanced Fully Depleted SOI n-MOSFETs

IEEE Electron Device Letters

In this letter, we demonstrate the existence of the source–drain series resistance mismatch and i... more In this letter, we demonstrate the existence of the source–drain series resistance mismatch and its impact on drain current variability with regard to the other mismatch parameters. To this end, we propose a new methodology for the drain current mismatch study based on YYY -function, enabling a precise determination of the various variability sources in advanced fully depleted silicon on insulator (SOI) MOS devices.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Full gate voltage range Lambert-function based methodology for FDSOI MOSFET parameter extraction

A new full gate voltage range methodology using a Lambert W function based inversion charge model... more A new full gate voltage range methodology using a Lambert W function based inversion charge model, for extracting the electrical parameters in FDSOI nano-MOSFET devices, has been developed. Split capacitance–voltage measurements carried out on 14 nm technology FDSOI devices show that the inversion charge variation with gate voltage can be well described by a Lambert W function. Based on the drain current equation in the linear region including the inversion charge described by the Lambert function of gate voltage and the standard mobility equation enables five electrical MOSFET parameters to be extracted from experimental Id–Vg measurements (ideality factor, threshold voltage, low field mobility, first and second order mobility attenuation factors). The extracted parameters were compared with those extracted by the well-known Y-function in strong inversion region. The present methodology for extracting the electrical MOSFET parameters was verified over a wide range of channel length...

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Research paper thumbnail of New LFN and RTN analysis methodology in 28 and 14nm FD-SOI MOSFETs

2015 IEEE International Reliability Physics Symposium, 2015

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Research paper thumbnail of Drain-Current Flicker Noise Modeling in nMOSFETs From a 14-nm FDSOI Technology

IEEE Transactions on Electron Devices, 2015

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Research paper thumbnail of Impact of low-frequency noise variability on statistical parameter extraction in ultra-scaled CMOS devices

Electronics Letters

The impact on the extracted low-frequency noise (LFN) parameter values due to LFN variability in ... more The impact on the extracted low-frequency noise (LFN) parameter values due to LFN variability in CMOS devices is investigated. First, it is demonstrated that the noise level dispersion follows a log normal statistical distribution. Then, based on this feature, it is explained why the mean values from the linear data are different from the mean values (or median values) calculated from the log noise data. Finally, the consequence of this finding in terms of LFN characterisation issues and Monte Carlo LFN variability circuit simulation is discussed.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Impact of front-back gate coupling on low frequency noise in 28 nm FDSOI MOSFETs

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2012

ABSTRACT Low-frequency (LF) noise has been studied on 28 nm FDSOI devices with ultra-thin silicon... more ABSTRACT Low-frequency (LF) noise has been studied on 28 nm FDSOI devices with ultra-thin silicon film (7 nm) and thin buried oxide (25 nm). A strong dependence of the noise level on the combination of the front and back biasing voltages was observed, and justified by the coupling effect of both Si/High-K dielectric and Si/SiO2 interface noise sources (channel/front oxide and channel/buried oxide), combined with the change of the Remote Coulomb scattering. From comparisons of the experimental and simulation results, it is shown that the main reason of this dependence is the distance of the charge distribution centroid from the interfaces, which is controlled by both front and back-gate bias voltages, and the way this distance affects the Remote Coulomb scattering coefficient a. A new LF noise model approach is proposed to include all these effects. This also allows us to assess the oxide trap density values for both interfaces.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of A new linear voltage-to-current converter with threshold voltage compensation for analog circuits applications in polycrystalline silicon TFT process

A new linear voltage-to-current (V-I) converter with threshold voltage compensation for analog ci... more A new linear voltage-to-current (V-I) converter with threshold voltage compensation for analog circuits design implemented with low-temperature polycrystalline silicon thin-film transistors (LT poly-Si TFTs) is proposed. The proposed V-I converter has been verified through simulations with Synopsys HSpice using level 62 RPI model. In order to obtain realistic simulations, parameters extraction in fabricated LT poly-Si TFTs was made. The proposed

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Low-frequency noise behavior of n-channel UTBB FD-SOI MOSFETs

2013 22nd International Conference on Noise and Fluctuations (ICNF), 2013

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Research paper thumbnail of Short Channel Effects on LTPS TFT Degradation

Journal of Display Technology, 2013

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Research paper thumbnail of Evolution of low frequency noise and noise variability through CMOS bulk technology nodes from 0.5μm down to 20nm

Solid-State Electronics, 2014

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Origin of the low-frequency noise in n-channel FinFETs

Solid-State Electronics, 2013

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Symmetrical unified compact model of short-channel double-gate MOSFETs

Solid-State Electronics, 2012

ABSTRACT An explicit charge-based unified compact drain current model for lightly doped or undope... more ABSTRACT An explicit charge-based unified compact drain current model for lightly doped or undoped DG MOSFETs is proposed. It takes into account the short-channel effects, the subthreshold slope degradation, the drain-induced barrier lowering and the channel length modulation effects. The model is valid and continuous in all regimes of operation and it has been validated by developing a Verilog-A code and comparing the model results of transfer and output characteristics with simulation results exhibiting an average error of about 3%. The efficient solution of the Lambert W function for the inversion charge and the symmetry of the model make it suitable for circuit simulation and allow fast and accurate simulations of the transistor characteristics.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Analytical low-frequency noise model in the linear region of lightly doped nanoscale double-gate metal-oxide-semiconductor field-effect transistors

Journal of Applied Physics, 2010

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Low-Frequency Noise Sources in Advanced UTBB FD-SOI MOSFETs

IEEE Transactions on Electron Devices, 2000

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Analytical Modeling of Threshold Voltage and Interface Ideality Factor of Nanoscale Ultrathin Body and Buried Oxide SOI MOSFETs With Back Gate Control

IEEE Transactions on Electron Devices, 2000

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Origin of Low-Frequency Noise in the Low Drain Current Range of Bottom-Gate Amorphous IGZO Thin-Film Transistors

IEEE Electron Device Letters, 2000

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