Christoforos Theodorou - Academia.edu (original) (raw)

Papers by Christoforos Theodorou

The dynamic variation in memory devices such as the Static Random Access Memory can give errors i... more The dynamic variation in memory devices such as the Static Random Access Memory can give errors in read or write operations. In this paper, the effect of low-frequency and random telegraph noise on the dynamic variation of one SRAM cell is detailed. The effect on circuit noise, speed, and length of time of processing is examined, using the Supply Read Retention Voltage and the Read Static Noise Margin. New test run methods are also developed. The obtained results simulation shows the importance of noise caused by dynamic variation, and the impact of Random Telegraph noise on SRAM variability is examined by evaluating the statistical distributions of Random Telegraph noise amplitude in the pull-up, pull-down. The threshold voltage mismatch between neighboring cell transistors due to intrinsic fluctuations typically contributes to larger reductions in static noise margin. Also the contribution of each of the SRAM transistor to total dynamic variation has been identified.

Introduction: A crucial issue in MOSFETs and especially in advanced nano-scaled devices is the ex... more Introduction: A crucial issue in MOSFETs and especially in advanced nano-scaled devices is the extraction of their electrical parameters [1]. Recently, we developed a new methodology based on a Lambert W (LW) function for the inversion charge to extract the parameters of nano-scale FD-SOI MOSFETs [2]. The advantage of our methodology is the fact that in contrast with the existing techniques [3], it exploits the entire gate voltage range from weak to strong inversion, i.e. V g = OV to V dd. This method has already been confirmed at zero back bias voltage in [2]. Here, we present a validation of the new approach for a wide range of back bias voltage and different channel lengths, followed by an overview of the extracted parameters properties.

Solid-State Electronics, 2015

The impact of the dynamic variability due to low frequency and RTN fluctuations on single MOSFET ... more The impact of the dynamic variability due to low frequency and RTN fluctuations on single MOSFET operation from 14 nm FD-SOI technology is investigated for the first time. It is shown that the dynamic variability is enhanced as the rise time and the device area are reduced. Different simulation approaches were investigated to determine the best methodology for simulating the dynamic variability in Cadence circuit simulation tool. It is demonstrated that Monte-Carlo and periodic transient noise simulations are methodologies capable to reproduce accurately dynamic variability in Cadence.

In this paper, we performed a statistical analysis of the low-frequency noise (LFN) in 14nm FDSOI... more In this paper, we performed a statistical analysis of the low-frequency noise (LFN) in 14nm FDSOI n-MOS devices. Front and back gate interfaces were characterized, revealing an equal contribution to the total noise level. Finally, the LFN variability is analyzed and a comparison to previous CMOS technologies is presented.

IEEE Electron Device Letters

In this letter, we demonstrate the existence of the source–drain series resistance mismatch and i... more In this letter, we demonstrate the existence of the source–drain series resistance mismatch and its impact on drain current variability with regard to the other mismatch parameters. To this end, we propose a new methodology for the drain current mismatch study based on YYY -function, enabling a precise determination of the various variability sources in advanced fully depleted silicon on insulator (SOI) MOS devices.

A new full gate voltage range methodology using a Lambert W function based inversion charge model... more A new full gate voltage range methodology using a Lambert W function based inversion charge model, for extracting the electrical parameters in FDSOI nano-MOSFET devices, has been developed. Split capacitance–voltage measurements carried out on 14 nm technology FDSOI devices show that the inversion charge variation with gate voltage can be well described by a Lambert W function. Based on the drain current equation in the linear region including the inversion charge described by the Lambert function of gate voltage and the standard mobility equation enables five electrical MOSFET parameters to be extracted from experimental Id–Vg measurements (ideality factor, threshold voltage, low field mobility, first and second order mobility attenuation factors). The extracted parameters were compared with those extracted by the well-known Y-function in strong inversion region. The present methodology for extracting the electrical MOSFET parameters was verified over a wide range of channel length...

2015 IEEE International Reliability Physics Symposium, 2015

A thorough investigation and statistical analysis of the low-frequency (LFN) and random telegraph... more A thorough investigation and statistical analysis of the low-frequency (LFN) and random telegraph noise (RTN) in 28 and 14nm FD-SOI CMOS transistors is presented, for the first time. It is shown that the 14nm technology node is improved in terms of threshold voltage fluctuations when compared to the 28nm one. A new analysis method that directly probes the RTN presence is also proposed. Finally, the LFN/RTN impact on the device dynamic variability is presented through CADENCE design suite circuit simulations.

IEEE Transactions on Electron Devices, 2015

Extensive investigation of the drain-current low-frequency noise in n-channel MOSFETs issued from... more Extensive investigation of the drain-current low-frequency noise in n-channel MOSFETs issued from a 14-nm fully depleted silicon-on-insulator technology node has been carried out. The results demonstrate that the carrier number fluctuation (CNF) with correlated mobility fluctuations (CMFs) model accurately and continuously describes the 1/ f noise from weak to strong inversion, from linear to saturation, and for all the back-bias conditions. It is shown that using only two parameters, i.e., the effective flat-band voltage spectral density S Vfb,eff and CMF factor eff , the CNF/CMF noise model can predict the transistor 1/ f noise level of all channel dimensions and under any bias conditions. Thus, it can be easily used in SPICE noise modeling for circuit simulations.

Electronics Letters

The impact on the extracted low-frequency noise (LFN) parameter values due to LFN variability in ... more The impact on the extracted low-frequency noise (LFN) parameter values due to LFN variability in CMOS devices is investigated. First, it is demonstrated that the noise level dispersion follows a log normal statistical distribution. Then, based on this feature, it is explained why the mean values from the linear data are different from the mean values (or median values) calculated from the log noise data. Finally, the consequence of this finding in terms of LFN characterisation issues and Monte Carlo LFN variability circuit simulation is discussed.

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2012

ABSTRACT Low-frequency (LF) noise has been studied on 28 nm FDSOI devices with ultra-thin silicon... more ABSTRACT Low-frequency (LF) noise has been studied on 28 nm FDSOI devices with ultra-thin silicon film (7 nm) and thin buried oxide (25 nm). A strong dependence of the noise level on the combination of the front and back biasing voltages was observed, and justified by the coupling effect of both Si/High-K dielectric and Si/SiO2 interface noise sources (channel/front oxide and channel/buried oxide), combined with the change of the Remote Coulomb scattering. From comparisons of the experimental and simulation results, it is shown that the main reason of this dependence is the distance of the charge distribution centroid from the interfaces, which is controlled by both front and back-gate bias voltages, and the way this distance affects the Remote Coulomb scattering coefficient a. A new LF noise model approach is proposed to include all these effects. This also allows us to assess the oxide trap density values for both interfaces.

A new linear voltage-to-current (V-I) converter with threshold voltage compensation for analog ci... more A new linear voltage-to-current (V-I) converter with threshold voltage compensation for analog circuits design implemented with low-temperature polycrystalline silicon thin-film transistors (LT poly-Si TFTs) is proposed. The proposed V-I converter has been verified through simulations with Synopsys HSpice using level 62 RPI model. In order to obtain realistic simulations, parameters extraction in fabricated LT poly-Si TFTs was made. The proposed

2013 22nd International Conference on Noise and Fluctuations (ICNF), 2013

The low-frequency noise (LFN) behavior of ultra thin body and buried oxide (UTBB) fully-depleted ... more The low-frequency noise (LFN) behavior of ultra thin body and buried oxide (UTBB) fully-depleted (FD) siliconon-insulator (SOI) n-channel MOSFETs has been explored, emphasizing on the contribution of the buried-oxide (BOX) and the Si-BOX interface to the total drain current noise level. In order to successfully distinguish the different noise sources, measurements under different front and back gate voltages were performed. The noise spectra for all bias conditions consist of both flicker and Lorentzian-type noise components. A fitting method was used to extract the parameters of the LFN. It is shown that the flicker noise follows the carrier number with correlated mobility fluctuations model at both interfaces and the Si/BOX interface contributes to the total LFN level, even without back gate bias voltage. The front and back gate voltage dependence of the Lorentzian time constants indicates a uniform distribution of generation-recombination (g-r) centers within the silicon film. In addition, when the Si/BOX interface is accumulated, interface traps at the front gate are activated due to higher front gate voltages, giving rise to a different type of g-r noise.

Journal of Display Technology, 2013

Double-gate (DG) polysilicon thin-film transistors (TFTs) are considered very important for futur... more Double-gate (DG) polysilicon thin-film transistors (TFTs) are considered very important for future large area electronics, due to their capability to electrically control TFT characteristics. The scope of this paper is to study how high performance DG polysilicon TFT degradation is affected by shrinking of the channel length. We applied equivalent dc stress in DG TFTs of different top gate length , with channel width m and bottom gate length fixed at m. Also, to ensure that we only see effects from the top gate operation, the bottom gate bias was kept constant at 3 V, pushing the carriers towards the top interface. Degradation seemed to be much more intense in the longer device, despite the scaling of the stress field. This could be attributed to the larger number of sub-boundaries and grain boundaries as increases, causing larger scattering of the carriers towards the top interface and larger grain-boundary state creation. Low frequency noise measurements support the conclusions regarding the proposed degradation mechanisms of DG polysilicon TFTs with shrinking channel length.

Solid-State Electronics, 2014

In this paper, we present a thorough investigation of low frequency noise (LFN) and statistical n... more In this paper, we present a thorough investigation of low frequency noise (LFN) and statistical noise variability through CMOS planar bulk technologies manufactured along the past 12 years and, for the first time, from the most recent 20 nm CMOS bulk technology node. The experimental results are well interpreted by the carrier number with correlated mobility fluctuation model. This enabled us to plot the evolution with time and technology generation of the oxide trap density N t as a function of equivalent oxide thickness (EOT). It appears that, with the device miniaturization, N t overall increases almost by two decades with decreasing the EOT thickness from 12 nm for the 0.5 lm node to 1.3 nm for the 20 nm node for n-and p-MOS. Despite this increase of the mean trap density N t , the LFN statistical variability has surprisingly been well controlled with the decrease of EOT and the increase of N t and even improved in 28 and 20 nm node.

Solid-State Electronics, 2013

The origin of the low-frequency noise is investigated in n-channel fin-shaped field-effect transi... more The origin of the low-frequency noise is investigated in n-channel fin-shaped field-effect transistors (Fin-FETs) in terms of the channel length and fin width. In long-channel and wide fin devices, the spectra are dominated by 1/f noise due to carrier number fluctuation, correlated with mobility fluctuations. In longchannel and narrow fin devices, the spectra are composed of both 1/f and excess generation-recombination (g-r) noise components. Analysis of the g-r noise parameters lead to the conclusion that the g-r noise originates from traps in the sidewall gate oxides and in a depletion region near the sidewall interfaces. In short-channel devices, the spectra show 1/f behavior in the weak inversion described by carrier number fluctuations and g-r noise component in the low drain current region, possibly originating from the source and drain contacts process.

Solid-State Electronics, 2012

ABSTRACT An explicit charge-based unified compact drain current model for lightly doped or undope... more ABSTRACT An explicit charge-based unified compact drain current model for lightly doped or undoped DG MOSFETs is proposed. It takes into account the short-channel effects, the subthreshold slope degradation, the drain-induced barrier lowering and the channel length modulation effects. The model is valid and continuous in all regimes of operation and it has been validated by developing a Verilog-A code and comparing the model results of transfer and output characteristics with simulation results exhibiting an average error of about 3%. The efficient solution of the Lambert W function for the inversion charge and the symmetry of the model make it suitable for circuit simulation and allow fast and accurate simulations of the transistor characteristics.

Journal of Applied Physics, 2010

An analytical model for the transconductance to drain current ratio ͑g m / I d ͒ of lightly doped... more An analytical model for the transconductance to drain current ratio ͑g m / I d ͒ of lightly doped nanoscale double-gate metal-oxide-semiconductor field-effect transistors ͑DG MOSFETs͒ has been developed in the weak inversion and from linear to saturation region, using the conductive path potential approach. The obtained analytical model for g m / I d in the weak inversion has been extended in the strong inversion and in the linear region including the short-channel effects, as well as the surface roughness scattering, series resistance, and saturation velocity effects. The obtained g m / I d model from weak to strong inversion has been verified by comparing simulation and experimental results of DG MOSFET with gate length 50 nm and it has been implemented in modeling the 1/f low-frequency noise. The introduced noise model has been validated by developing a Verilog-A transistor noise model, which is in good agreement with the experimental noise results of DG MOSFET with gate length 50 nm in the linear region from weak to strong inversion.

IEEE Transactions on Electron Devices, 2000

The low-frequency noise (LFN) sources in ultrathin body (8.7 nm) and buried oxide (10 nm) fully d... more The low-frequency noise (LFN) sources in ultrathin body (8.7 nm) and buried oxide (10 nm) fully depleted siliconon-insulator (UTBB FD-SOI) n-and p-channel MOSFETs are analyzed. Both flicker and Lorentzian-type noise were observed, showing a dependence on the channel dimensions and the front/back gate bias conditions. The flicker noise component can be described by the carrier number with correlated mobility fluctuations model considering contribution from both interfaces. The Lorentzian-type noise originates mainly from generationrecombination (g-r) traps in the Si film, uniformly distributed in thin layers next to the drain and source contacts, and in some cases from g-r traps located at the front Si/oxide interface.

IEEE Transactions on Electron Devices, 2000

An analytical compact model for the drain current of undoped or lightly doped nanoscale FinFETs w... more An analytical compact model for the drain current of undoped or lightly doped nanoscale FinFETs with trapezoidal cross section is proposed. The compact model of rectangular FinFETs is extended to trapezoidal FinFETs using equivalent nonplanar device parameters and corner effects. The model has been validated by comparing the results with those of 3-D numerical device simulations. The very good accuracy of the drain current and transcapacitances makes the proposed model suitable for implementation in circuit simulation tools.

IEEE Electron Device Letters, 2000

The low-frequency noise of bottom-gate amorphous IGZO thin-film transistors is investigated in th... more The low-frequency noise of bottom-gate amorphous IGZO thin-film transistors is investigated in the low drain current range. The noise spectra show generation-recombination (g-r) noise at drain currents I d < 5 nA, attributed to bulk traps located in a thin layer of the IGZO close to the conducting channel. At higher drain currents, a pure 1/f noise is observed. It is shown that the carrier number fluctuations are responsible for the 1/f noise due to trapping/detrapping of carriers in slow oxide traps, located near the interface with uniform spatial distribution.

The dynamic variation in memory devices such as the Static Random Access Memory can give errors i... more The dynamic variation in memory devices such as the Static Random Access Memory can give errors in read or write operations. In this paper, the effect of low-frequency and random telegraph noise on the dynamic variation of one SRAM cell is detailed. The effect on circuit noise, speed, and length of time of processing is examined, using the Supply Read Retention Voltage and the Read Static Noise Margin. New test run methods are also developed. The obtained results simulation shows the importance of noise caused by dynamic variation, and the impact of Random Telegraph noise on SRAM variability is examined by evaluating the statistical distributions of Random Telegraph noise amplitude in the pull-up, pull-down. The threshold voltage mismatch between neighboring cell transistors due to intrinsic fluctuations typically contributes to larger reductions in static noise margin. Also the contribution of each of the SRAM transistor to total dynamic variation has been identified.

Introduction: A crucial issue in MOSFETs and especially in advanced nano-scaled devices is the ex... more Introduction: A crucial issue in MOSFETs and especially in advanced nano-scaled devices is the extraction of their electrical parameters [1]. Recently, we developed a new methodology based on a Lambert W (LW) function for the inversion charge to extract the parameters of nano-scale FD-SOI MOSFETs [2]. The advantage of our methodology is the fact that in contrast with the existing techniques [3], it exploits the entire gate voltage range from weak to strong inversion, i.e. V g = OV to V dd. This method has already been confirmed at zero back bias voltage in [2]. Here, we present a validation of the new approach for a wide range of back bias voltage and different channel lengths, followed by an overview of the extracted parameters properties.

Solid-State Electronics, 2015

The impact of the dynamic variability due to low frequency and RTN fluctuations on single MOSFET ... more The impact of the dynamic variability due to low frequency and RTN fluctuations on single MOSFET operation from 14 nm FD-SOI technology is investigated for the first time. It is shown that the dynamic variability is enhanced as the rise time and the device area are reduced. Different simulation approaches were investigated to determine the best methodology for simulating the dynamic variability in Cadence circuit simulation tool. It is demonstrated that Monte-Carlo and periodic transient noise simulations are methodologies capable to reproduce accurately dynamic variability in Cadence.

In this paper, we performed a statistical analysis of the low-frequency noise (LFN) in 14nm FDSOI... more In this paper, we performed a statistical analysis of the low-frequency noise (LFN) in 14nm FDSOI n-MOS devices. Front and back gate interfaces were characterized, revealing an equal contribution to the total noise level. Finally, the LFN variability is analyzed and a comparison to previous CMOS technologies is presented.

IEEE Electron Device Letters

In this letter, we demonstrate the existence of the source–drain series resistance mismatch and i... more In this letter, we demonstrate the existence of the source–drain series resistance mismatch and its impact on drain current variability with regard to the other mismatch parameters. To this end, we propose a new methodology for the drain current mismatch study based on YYY -function, enabling a precise determination of the various variability sources in advanced fully depleted silicon on insulator (SOI) MOS devices.

A new full gate voltage range methodology using a Lambert W function based inversion charge model... more A new full gate voltage range methodology using a Lambert W function based inversion charge model, for extracting the electrical parameters in FDSOI nano-MOSFET devices, has been developed. Split capacitance–voltage measurements carried out on 14 nm technology FDSOI devices show that the inversion charge variation with gate voltage can be well described by a Lambert W function. Based on the drain current equation in the linear region including the inversion charge described by the Lambert function of gate voltage and the standard mobility equation enables five electrical MOSFET parameters to be extracted from experimental Id–Vg measurements (ideality factor, threshold voltage, low field mobility, first and second order mobility attenuation factors). The extracted parameters were compared with those extracted by the well-known Y-function in strong inversion region. The present methodology for extracting the electrical MOSFET parameters was verified over a wide range of channel length...

2015 IEEE International Reliability Physics Symposium, 2015

A thorough investigation and statistical analysis of the low-frequency (LFN) and random telegraph... more A thorough investigation and statistical analysis of the low-frequency (LFN) and random telegraph noise (RTN) in 28 and 14nm FD-SOI CMOS transistors is presented, for the first time. It is shown that the 14nm technology node is improved in terms of threshold voltage fluctuations when compared to the 28nm one. A new analysis method that directly probes the RTN presence is also proposed. Finally, the LFN/RTN impact on the device dynamic variability is presented through CADENCE design suite circuit simulations.

IEEE Transactions on Electron Devices, 2015

Extensive investigation of the drain-current low-frequency noise in n-channel MOSFETs issued from... more Extensive investigation of the drain-current low-frequency noise in n-channel MOSFETs issued from a 14-nm fully depleted silicon-on-insulator technology node has been carried out. The results demonstrate that the carrier number fluctuation (CNF) with correlated mobility fluctuations (CMFs) model accurately and continuously describes the 1/ f noise from weak to strong inversion, from linear to saturation, and for all the back-bias conditions. It is shown that using only two parameters, i.e., the effective flat-band voltage spectral density S Vfb,eff and CMF factor eff , the CNF/CMF noise model can predict the transistor 1/ f noise level of all channel dimensions and under any bias conditions. Thus, it can be easily used in SPICE noise modeling for circuit simulations.

Electronics Letters

The impact on the extracted low-frequency noise (LFN) parameter values due to LFN variability in ... more The impact on the extracted low-frequency noise (LFN) parameter values due to LFN variability in CMOS devices is investigated. First, it is demonstrated that the noise level dispersion follows a log normal statistical distribution. Then, based on this feature, it is explained why the mean values from the linear data are different from the mean values (or median values) calculated from the log noise data. Finally, the consequence of this finding in terms of LFN characterisation issues and Monte Carlo LFN variability circuit simulation is discussed.

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2012

ABSTRACT Low-frequency (LF) noise has been studied on 28 nm FDSOI devices with ultra-thin silicon... more ABSTRACT Low-frequency (LF) noise has been studied on 28 nm FDSOI devices with ultra-thin silicon film (7 nm) and thin buried oxide (25 nm). A strong dependence of the noise level on the combination of the front and back biasing voltages was observed, and justified by the coupling effect of both Si/High-K dielectric and Si/SiO2 interface noise sources (channel/front oxide and channel/buried oxide), combined with the change of the Remote Coulomb scattering. From comparisons of the experimental and simulation results, it is shown that the main reason of this dependence is the distance of the charge distribution centroid from the interfaces, which is controlled by both front and back-gate bias voltages, and the way this distance affects the Remote Coulomb scattering coefficient a. A new LF noise model approach is proposed to include all these effects. This also allows us to assess the oxide trap density values for both interfaces.

A new linear voltage-to-current (V-I) converter with threshold voltage compensation for analog ci... more A new linear voltage-to-current (V-I) converter with threshold voltage compensation for analog circuits design implemented with low-temperature polycrystalline silicon thin-film transistors (LT poly-Si TFTs) is proposed. The proposed V-I converter has been verified through simulations with Synopsys HSpice using level 62 RPI model. In order to obtain realistic simulations, parameters extraction in fabricated LT poly-Si TFTs was made. The proposed

2013 22nd International Conference on Noise and Fluctuations (ICNF), 2013

The low-frequency noise (LFN) behavior of ultra thin body and buried oxide (UTBB) fully-depleted ... more The low-frequency noise (LFN) behavior of ultra thin body and buried oxide (UTBB) fully-depleted (FD) siliconon-insulator (SOI) n-channel MOSFETs has been explored, emphasizing on the contribution of the buried-oxide (BOX) and the Si-BOX interface to the total drain current noise level. In order to successfully distinguish the different noise sources, measurements under different front and back gate voltages were performed. The noise spectra for all bias conditions consist of both flicker and Lorentzian-type noise components. A fitting method was used to extract the parameters of the LFN. It is shown that the flicker noise follows the carrier number with correlated mobility fluctuations model at both interfaces and the Si/BOX interface contributes to the total LFN level, even without back gate bias voltage. The front and back gate voltage dependence of the Lorentzian time constants indicates a uniform distribution of generation-recombination (g-r) centers within the silicon film. In addition, when the Si/BOX interface is accumulated, interface traps at the front gate are activated due to higher front gate voltages, giving rise to a different type of g-r noise.

Journal of Display Technology, 2013

Double-gate (DG) polysilicon thin-film transistors (TFTs) are considered very important for futur... more Double-gate (DG) polysilicon thin-film transistors (TFTs) are considered very important for future large area electronics, due to their capability to electrically control TFT characteristics. The scope of this paper is to study how high performance DG polysilicon TFT degradation is affected by shrinking of the channel length. We applied equivalent dc stress in DG TFTs of different top gate length , with channel width m and bottom gate length fixed at m. Also, to ensure that we only see effects from the top gate operation, the bottom gate bias was kept constant at 3 V, pushing the carriers towards the top interface. Degradation seemed to be much more intense in the longer device, despite the scaling of the stress field. This could be attributed to the larger number of sub-boundaries and grain boundaries as increases, causing larger scattering of the carriers towards the top interface and larger grain-boundary state creation. Low frequency noise measurements support the conclusions regarding the proposed degradation mechanisms of DG polysilicon TFTs with shrinking channel length.

Solid-State Electronics, 2014

In this paper, we present a thorough investigation of low frequency noise (LFN) and statistical n... more In this paper, we present a thorough investigation of low frequency noise (LFN) and statistical noise variability through CMOS planar bulk technologies manufactured along the past 12 years and, for the first time, from the most recent 20 nm CMOS bulk technology node. The experimental results are well interpreted by the carrier number with correlated mobility fluctuation model. This enabled us to plot the evolution with time and technology generation of the oxide trap density N t as a function of equivalent oxide thickness (EOT). It appears that, with the device miniaturization, N t overall increases almost by two decades with decreasing the EOT thickness from 12 nm for the 0.5 lm node to 1.3 nm for the 20 nm node for n-and p-MOS. Despite this increase of the mean trap density N t , the LFN statistical variability has surprisingly been well controlled with the decrease of EOT and the increase of N t and even improved in 28 and 20 nm node.

Solid-State Electronics, 2013

The origin of the low-frequency noise is investigated in n-channel fin-shaped field-effect transi... more The origin of the low-frequency noise is investigated in n-channel fin-shaped field-effect transistors (Fin-FETs) in terms of the channel length and fin width. In long-channel and wide fin devices, the spectra are dominated by 1/f noise due to carrier number fluctuation, correlated with mobility fluctuations. In longchannel and narrow fin devices, the spectra are composed of both 1/f and excess generation-recombination (g-r) noise components. Analysis of the g-r noise parameters lead to the conclusion that the g-r noise originates from traps in the sidewall gate oxides and in a depletion region near the sidewall interfaces. In short-channel devices, the spectra show 1/f behavior in the weak inversion described by carrier number fluctuations and g-r noise component in the low drain current region, possibly originating from the source and drain contacts process.

Solid-State Electronics, 2012

ABSTRACT An explicit charge-based unified compact drain current model for lightly doped or undope... more ABSTRACT An explicit charge-based unified compact drain current model for lightly doped or undoped DG MOSFETs is proposed. It takes into account the short-channel effects, the subthreshold slope degradation, the drain-induced barrier lowering and the channel length modulation effects. The model is valid and continuous in all regimes of operation and it has been validated by developing a Verilog-A code and comparing the model results of transfer and output characteristics with simulation results exhibiting an average error of about 3%. The efficient solution of the Lambert W function for the inversion charge and the symmetry of the model make it suitable for circuit simulation and allow fast and accurate simulations of the transistor characteristics.

Journal of Applied Physics, 2010

An analytical model for the transconductance to drain current ratio ͑g m / I d ͒ of lightly doped... more An analytical model for the transconductance to drain current ratio ͑g m / I d ͒ of lightly doped nanoscale double-gate metal-oxide-semiconductor field-effect transistors ͑DG MOSFETs͒ has been developed in the weak inversion and from linear to saturation region, using the conductive path potential approach. The obtained analytical model for g m / I d in the weak inversion has been extended in the strong inversion and in the linear region including the short-channel effects, as well as the surface roughness scattering, series resistance, and saturation velocity effects. The obtained g m / I d model from weak to strong inversion has been verified by comparing simulation and experimental results of DG MOSFET with gate length 50 nm and it has been implemented in modeling the 1/f low-frequency noise. The introduced noise model has been validated by developing a Verilog-A transistor noise model, which is in good agreement with the experimental noise results of DG MOSFET with gate length 50 nm in the linear region from weak to strong inversion.

IEEE Transactions on Electron Devices, 2000

The low-frequency noise (LFN) sources in ultrathin body (8.7 nm) and buried oxide (10 nm) fully d... more The low-frequency noise (LFN) sources in ultrathin body (8.7 nm) and buried oxide (10 nm) fully depleted siliconon-insulator (UTBB FD-SOI) n-and p-channel MOSFETs are analyzed. Both flicker and Lorentzian-type noise were observed, showing a dependence on the channel dimensions and the front/back gate bias conditions. The flicker noise component can be described by the carrier number with correlated mobility fluctuations model considering contribution from both interfaces. The Lorentzian-type noise originates mainly from generationrecombination (g-r) traps in the Si film, uniformly distributed in thin layers next to the drain and source contacts, and in some cases from g-r traps located at the front Si/oxide interface.

IEEE Transactions on Electron Devices, 2000

An analytical compact model for the drain current of undoped or lightly doped nanoscale FinFETs w... more An analytical compact model for the drain current of undoped or lightly doped nanoscale FinFETs with trapezoidal cross section is proposed. The compact model of rectangular FinFETs is extended to trapezoidal FinFETs using equivalent nonplanar device parameters and corner effects. The model has been validated by comparing the results with those of 3-D numerical device simulations. The very good accuracy of the drain current and transcapacitances makes the proposed model suitable for implementation in circuit simulation tools.

IEEE Electron Device Letters, 2000

The low-frequency noise of bottom-gate amorphous IGZO thin-film transistors is investigated in th... more The low-frequency noise of bottom-gate amorphous IGZO thin-film transistors is investigated in the low drain current range. The noise spectra show generation-recombination (g-r) noise at drain currents I d < 5 nA, attributed to bulk traps located in a thin layer of the IGZO close to the conducting channel. At higher drain currents, a pure 1/f noise is observed. It is shown that the carrier number fluctuations are responsible for the 1/f noise due to trapping/detrapping of carriers in slow oxide traps, located near the interface with uniform spatial distribution.