Tushar Negi - Academia.edu (original) (raw)
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Papers by Tushar Negi
Pipelining is a technique of decomposing a sequential process into sub-operations, with each sub ... more Pipelining is a technique of decomposing a sequential process into sub-operations, with each sub process being divided segment that operates concurrently with all other segments. A pipeline may be visualized as a collection of processing segments through which binary information flows. Each segment performs partial processing segments dictated by the way the task is partitioned. The result obtained in one segment is transferred to subsequent segments in each step. The final result is obtained after the data has passed through all segments.This paper develops a code for the implementation of an 8-Bit microprocessor which implements instruction pipelining. After synthesis, an FPGA realization may be obtained . Simulation using Xilinx and ModelSim also produces favourable results which showcase the speedup (in terms of time) to carry out a program as compared to a non-pipelined version of this microprocessor.
ISRN Electronics, 2013
Current difference buffered amplifier (CDBA) based universal inverse filter configuration is prop... more Current difference buffered amplifier (CDBA) based universal inverse filter configuration is proposed. The topology can be used to synthesize inverse low-pass (ILP), inverse high-pass (IHP), inverse band-pass (IBP), inverse band-reject (IBR), and inverse all-pass filter functions with appropriate admittance choices. Workability of the proposed universal inverse filter configuration is demonstrated through PSPICE simulations for which CDBA is realized using current feedback operational amplifier (CFOA). The simulation results are found in close agreement with the theoretical results.
Pipelining is a technique of decomposing a sequential process into sub-operations, with each sub ... more Pipelining is a technique of decomposing a sequential process into sub-operations, with each sub process being divided segment that operates concurrently with all other segments. A pipeline may be visualized as a collection of processing segments through which binary information flows. Each segment performs partial processing segments dictated by the way the task is partitioned. The result obtained in one segment is transferred to subsequent segments in each step. The final result is obtained after the data has passed through all segments.This paper develops a code for the implementation of an 8-Bit microprocessor which implements instruction pipelining. After synthesis, an FPGA realization may be obtained . Simulation using Xilinx and ModelSim also produces favourable results which showcase the speedup (in terms of time) to carry out a program as compared to a non-pipelined version of this microprocessor.
ISRN Electronics, 2013
Current difference buffered amplifier (CDBA) based universal inverse filter configuration is prop... more Current difference buffered amplifier (CDBA) based universal inverse filter configuration is proposed. The topology can be used to synthesize inverse low-pass (ILP), inverse high-pass (IHP), inverse band-pass (IBP), inverse band-reject (IBR), and inverse all-pass filter functions with appropriate admittance choices. Workability of the proposed universal inverse filter configuration is demonstrated through PSPICE simulations for which CDBA is realized using current feedback operational amplifier (CFOA). The simulation results are found in close agreement with the theoretical results.