Gregory Uehara - Academia.edu (original) (raw)

Papers by Gregory Uehara

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143)

ABSTRACT This paper describes a monolithic fixed equalizer/slicer combination for high speed comm... more ABSTRACT This paper describes a monolithic fixed equalizer/slicer combination for high speed communication over low-cost light-weight RG-316 coaxial cable. Measured data shows the equalizer/slicer effective for cable lengths up to 30 feet with data rates of 1.3, 5, and 10 Gbps. The equalizer/detector block consumes 83 mW from a -5.2 V supply and is implemented in a 1 μm GaAs HBT technology

A new architecture for digital implementation of the adapti ve equalizer in Class IV P artialResp... more A new architecture for digital implementation of the adapti ve equalizer in Class IV P artialResponse Maximum Likelihood (PRML) channels emplo ying parallelism and pipelining is described. The architecture was used in a prototype inte grated circuit in a 1.2 um CMOS tech-nology to implement an 8-tap adaptive equalizer and Viterbi sequence detector which consumes a total of 70 mW from a 3.3 V supply operating at an input sampling rate of 50 MHz.

Block codes have trellis structures and decoders amenable to high speed CMOS VLSI implementation.... more Block codes have trellis structures and decoders amenable to high speed CMOS VLSI implementation. For a given CMOS technology, these structures enable operating speeds higher than those achievable using convolutional codes for only modest reductions in coding gain. As a result, block codes have tremendous potential for satellite trunk and other future high-speed communication applications. This paper describes a new approach for implementation of the synchronization function for block codes. The approach utilizes the output of the Viterbi decoder and therefore employs the strength of the decoder. Its operation requires no knowledge of the signal-to-noise ratio of the received signal, has a simple implementation, adds no overhead to the transmitted data, and has been shown to be effective in simulation for received SNR greater than 2 dB.

A (64,40,8) subcode of the (64,42,8) third-order Reed-Muller code is proposed to NASA for high-sp... more A (64,40,8) subcode of the (64,42,8) third-order Reed-Muller code is proposed to NASA for high-speed satellite communications. This code can be either used alone or used as an inner-code in a concatenated coding system with the NASA standard (255,223,33) Reed-Solomon code as the outer code to achieve high performance with reduced decoding complexity. This Reed-Muller subcode has a relatively simple and parallel trellis structure and consequently can be decoded with a group of identical and relatively simple Viterbi decoders in parallel to achieve high-speed decoding. In this report, the complexities of various sectionalized trellis diagrams are analyzed. Based on this analysis, the trellis diagram with the smallest overall complexity will be used for the implementation of a high-speed decoder.

L'invention concerne un systeme comprenant un premier module d'horloge concu pour generer... more L'invention concerne un systeme comprenant un premier module d'horloge concu pour generer une premiere reference d'horloge qui n'est pas corrigee a l'aide d'une correction de frequence automatique (AFC). Un module de systeme de positionnement global (GPS) est concu pour recevoir la premiere reference d'horloge. Un circuit integre d'un emetteur-recepteur cellulaire comprend une boucle de verrouillage de phase de systeme concue pour recevoir la premiere reference d'horloge, executer l'AFC et generer une seconde reference d'horloge qui est corrigee par l'AFC.

Des aspects de l'invention portent sur un amplificateur a transconductance passe-bande qui pe... more Des aspects de l'invention portent sur un amplificateur a transconductance passe-bande qui peut comprendre un amplificateur a transconductance de diminuende qui convertit un signal de tension en un premier courant et un amplificateur a transconductance de diminuteur qui convertit le signal de tension en un second courant ayant sensiblement la meme amplitude que le premier courant mais de polarite opposee aussi bien dans une premiere que dans une seconde bandes attenuees. Le second courant peut avoir une amplitude sensiblement inferieure a celle du premier courant dans une bande passante. L'amplificateur a transconductance passe-bande decrit peut egalement comprendre un controleur qui peut accorder la bande passante et les bandes attenuees et un circuit d'addition qui peut additionner le premier courant et le second courant.

Block codes have trellis structures and decoders amenable to high speed CMOS VLSI implementation.... more Block codes have trellis structures and decoders amenable to high speed CMOS VLSI implementation. For a given CMOS technology, these structures enable operating speeds higher than those achievable using convolutional codes for only modest reductions in coding gain. As a result, block codes have tremendous potential for satellite trunk and other future high-speed communication applications. This paper describes a new approach for implementation of the synchronization function for block codes. The approach utilizes the output of the Viterbi decoder and therefore employs the strength of the decoder. Its operation requires no knowledge of the signal-to-noise ratio of the received signal, has a simple implementation, adds no overhead to the transmitted data, and has been shown to be effective in simulation for received SNR greater than 2 dB.

custom integrated circuits conference, May 11, 1998

This paper describes circuit techniques for the implementation of low-voltage CMOS integrators fo... more This paper describes circuit techniques for the implementation of low-voltage CMOS integrators for continuous-time filters. A prototype sixth-order Butterworth lowpass filter with two programmable zeros was designed and developed to demonstrate the proposed techniques. The filter is suitable for magnetic disk read channel applications and achieves a 4.8:1 bandwidth tuning range with a maximum -3 dB bandwidth of 130 MHz. The spurious free dynamic range for an input signal of 300 mV peak-to-peak differential is greater than 40 dB. The prototype filter alone consumes 130 mW from a 3.0 V supply and is implemented in a 0.35 /spl mu/m CMOS technology.

international symposium on circuits and systems, May 10, 1992

A new approach for monolithic CMOS implementation of the low-pass filter function in analog front... more A new approach for monolithic CMOS implementation of the low-pass filter function in analog front-ends for receivers in high speed data communications applications is presented. The approach is based on switched-capacitor transversal filter structures employing parallelism and pipelining to increase throughput. Architectures appropriate for filters with both short and long impulse responses are presented along with necessary hardware requirements. Limitations and the effect of non-idealities on the proposed approach are also discussed.<<ETX>>

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143)

ABSTRACT This paper describes a monolithic fixed equalizer/slicer combination for high speed comm... more ABSTRACT This paper describes a monolithic fixed equalizer/slicer combination for high speed communication over low-cost light-weight RG-316 coaxial cable. Measured data shows the equalizer/slicer effective for cable lengths up to 30 feet with data rates of 1.3, 5, and 10 Gbps. The equalizer/detector block consumes 83 mW from a -5.2 V supply and is implemented in a 1 μm GaAs HBT technology

A new architecture for digital implementation of the adapti ve equalizer in Class IV P artialResp... more A new architecture for digital implementation of the adapti ve equalizer in Class IV P artialResponse Maximum Likelihood (PRML) channels emplo ying parallelism and pipelining is described. The architecture was used in a prototype inte grated circuit in a 1.2 um CMOS tech-nology to implement an 8-tap adaptive equalizer and Viterbi sequence detector which consumes a total of 70 mW from a 3.3 V supply operating at an input sampling rate of 50 MHz.

Block codes have trellis structures and decoders amenable to high speed CMOS VLSI implementation.... more Block codes have trellis structures and decoders amenable to high speed CMOS VLSI implementation. For a given CMOS technology, these structures enable operating speeds higher than those achievable using convolutional codes for only modest reductions in coding gain. As a result, block codes have tremendous potential for satellite trunk and other future high-speed communication applications. This paper describes a new approach for implementation of the synchronization function for block codes. The approach utilizes the output of the Viterbi decoder and therefore employs the strength of the decoder. Its operation requires no knowledge of the signal-to-noise ratio of the received signal, has a simple implementation, adds no overhead to the transmitted data, and has been shown to be effective in simulation for received SNR greater than 2 dB.

A (64,40,8) subcode of the (64,42,8) third-order Reed-Muller code is proposed to NASA for high-sp... more A (64,40,8) subcode of the (64,42,8) third-order Reed-Muller code is proposed to NASA for high-speed satellite communications. This code can be either used alone or used as an inner-code in a concatenated coding system with the NASA standard (255,223,33) Reed-Solomon code as the outer code to achieve high performance with reduced decoding complexity. This Reed-Muller subcode has a relatively simple and parallel trellis structure and consequently can be decoded with a group of identical and relatively simple Viterbi decoders in parallel to achieve high-speed decoding. In this report, the complexities of various sectionalized trellis diagrams are analyzed. Based on this analysis, the trellis diagram with the smallest overall complexity will be used for the implementation of a high-speed decoder.

L'invention concerne un systeme comprenant un premier module d'horloge concu pour generer... more L'invention concerne un systeme comprenant un premier module d'horloge concu pour generer une premiere reference d'horloge qui n'est pas corrigee a l'aide d'une correction de frequence automatique (AFC). Un module de systeme de positionnement global (GPS) est concu pour recevoir la premiere reference d'horloge. Un circuit integre d'un emetteur-recepteur cellulaire comprend une boucle de verrouillage de phase de systeme concue pour recevoir la premiere reference d'horloge, executer l'AFC et generer une seconde reference d'horloge qui est corrigee par l'AFC.

Des aspects de l'invention portent sur un amplificateur a transconductance passe-bande qui pe... more Des aspects de l'invention portent sur un amplificateur a transconductance passe-bande qui peut comprendre un amplificateur a transconductance de diminuende qui convertit un signal de tension en un premier courant et un amplificateur a transconductance de diminuteur qui convertit le signal de tension en un second courant ayant sensiblement la meme amplitude que le premier courant mais de polarite opposee aussi bien dans une premiere que dans une seconde bandes attenuees. Le second courant peut avoir une amplitude sensiblement inferieure a celle du premier courant dans une bande passante. L'amplificateur a transconductance passe-bande decrit peut egalement comprendre un controleur qui peut accorder la bande passante et les bandes attenuees et un circuit d'addition qui peut additionner le premier courant et le second courant.

Block codes have trellis structures and decoders amenable to high speed CMOS VLSI implementation.... more Block codes have trellis structures and decoders amenable to high speed CMOS VLSI implementation. For a given CMOS technology, these structures enable operating speeds higher than those achievable using convolutional codes for only modest reductions in coding gain. As a result, block codes have tremendous potential for satellite trunk and other future high-speed communication applications. This paper describes a new approach for implementation of the synchronization function for block codes. The approach utilizes the output of the Viterbi decoder and therefore employs the strength of the decoder. Its operation requires no knowledge of the signal-to-noise ratio of the received signal, has a simple implementation, adds no overhead to the transmitted data, and has been shown to be effective in simulation for received SNR greater than 2 dB.

custom integrated circuits conference, May 11, 1998

This paper describes circuit techniques for the implementation of low-voltage CMOS integrators fo... more This paper describes circuit techniques for the implementation of low-voltage CMOS integrators for continuous-time filters. A prototype sixth-order Butterworth lowpass filter with two programmable zeros was designed and developed to demonstrate the proposed techniques. The filter is suitable for magnetic disk read channel applications and achieves a 4.8:1 bandwidth tuning range with a maximum -3 dB bandwidth of 130 MHz. The spurious free dynamic range for an input signal of 300 mV peak-to-peak differential is greater than 40 dB. The prototype filter alone consumes 130 mW from a 3.0 V supply and is implemented in a 0.35 /spl mu/m CMOS technology.

international symposium on circuits and systems, May 10, 1992

A new approach for monolithic CMOS implementation of the low-pass filter function in analog front... more A new approach for monolithic CMOS implementation of the low-pass filter function in analog front-ends for receivers in high speed data communications applications is presented. The approach is based on switched-capacitor transversal filter structures employing parallelism and pipelining to increase throughput. Architectures appropriate for filters with both short and long impulse responses are presented along with necessary hardware requirements. Limitations and the effect of non-idealities on the proposed approach are also discussed.<<ETX>>