V. Hahanov - Academia.edu (original) (raw)

Papers by V. Hahanov

Research paper thumbnail of Fault cubic simulation for digital devices

Methods and models of a digital circuit analysis for test generation and fault simulation are off... more Methods and models of a digital circuit analysis for test generation and fault simulation are offered. The two-frame cubic algebra for compact cubic coverings of sequential primitive design, faulty and fault-free simulation of digital circuits is used. Problems of digital circuits testing are formalized as linear equations. The cubic method of primitive fault simulation, which allows: to transport input fault lists to primitive outputs; to generate analytical equations for digital circuit deductive simulation of the gate, functional and algorithmic description levels.

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Research paper thumbnail of Embedded SOC F-IP diagnosis by using algebraic logical method

... functional modes (Pc): }. T,T, T,T, T,T,T,T{T , P)T(P;F)T(F RC 8 DF 7 ME 6 BS 5 AD 4 SP 3 SA ... more ... functional modes (Pc): }. T,T, T,T, T,T,T,T{T , P)T(P;F)T(F RC 8 DF 7 ME 6 BS 5 AD 4 SP 3 SA 2 PR 1 c min minn 1i i c c min minn 1i i c = ≥ ≥ = = 1) Generalized structure of Testbench synthesis [1] is represented in Fig. 2 and ...

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Research paper thumbnail of Embedded SOC F-IP diagnosis by using algebraic logical method

... functional modes (Pc): }. T,T, T,T, T,T,T,T{T , P)T(P;F)T(F RC 8 DF 7 ME 6 BS 5 AD 4 SP 3 SA ... more ... functional modes (Pc): }. T,T, T,T, T,T,T,T{T , P)T(P;F)T(F RC 8 DF 7 ME 6 BS 5 AD 4 SP 3 SA 2 PR 1 c min minn 1i i c c min minn 1i i c = ≥ ≥ = = 1) Generalized structure of Testbench synthesis [1] is represented in Fig. 2 and ...

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Research paper thumbnail of Diagnosis and repair method of SoC memory

WSEAS transactions on …, 2008

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Research paper thumbnail of Algebra-logical diagnosis model for SoC F-IP

WSEAS transactions on …, 2008

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Research paper thumbnail of ISSN 1392-1215 ELECTRONICS AND ELECTRICAL ENGINEERING. 2008. No. 5 (85)

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Research paper thumbnail of Test generation and fault simulation methods on the basis of cubic algebra for digital devices

Proceedings Euromicro Symposium on Digital Systems Design, 2000

ABSTRACT

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Research paper thumbnail of Optimal embedded repairing of SOC memory

ABSTRACT

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Research paper thumbnail of Fault Coverage Improving Based on Testability Analysis of the VHDL Code

2007 9th International Conference - The Experience of Designing and Applications of CAD Systems in Microelectronics, 2007

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Research paper thumbnail of Parallel Logic Simulation using Multi-Core Workstations

2007 9th International Conference - The Experience of Designing and Applications of CAD Systems in Microelectronics, 2007

Existing software in Electronic Design Automation shows lack of dual-core processors support. As ... more Existing software in Electronic Design Automation shows lack of dual-core processors support. As a result, we see bad processing resources utilization. This work is devoted to exploration of existing approaches to parallel logic and fault simulation on dual-core workstations.

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Research paper thumbnail of Structural analysis for digital devices for the simulation system

The Experience of Designing and Application of CAD Systems in Microelectronics, 2003. CADSM 2003. Proceedings of the 7th International Conference., 2003

ABSTRACT

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Research paper thumbnail of Verification Of Digital System By A New Asserting Mechanism Based On Ieee 1500 Sect Standard

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006., 2006

ABSTRACT

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Research paper thumbnail of Embedded Method of Soc Memory Repairing

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Research paper thumbnail of Embedded Method of SoC Diagnosis

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Research paper thumbnail of Algebra-logical method for SOC embedded memory repair

Algebra-logical method of optimal memory repair based on the faults covering problem solving via ... more Algebra-logical method of optimal memory repair based on the faults covering problem solving via spare components using Boolean algebra is offered. The method enables to carry out the memory repair automatically in the operating process through embedded hardware or software implementation - a service infrastructure Intellectual Property module for fault repairing.

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Research paper thumbnail of Backtraced deductive-parallel fault simulation for digital circuits

The Experience of Designing and Application of CAD Systems in Microelectronics, 2003. CADSM 2003. Proceedings of the 7th International Conference., 2003

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Research paper thumbnail of Metrics of vector logic algebra for cyber space

2010 East-West Design & Test Symposium (EWDTS), 2010

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Research paper thumbnail of Intelligent Road Control and Monitoring

Lecture Notes in Electrical Engineering, 2013

ABSTRACT

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Research paper thumbnail of Deterministic method of genetic algorithms of test generation for digital systems verification

Modern Problems of Radio Engineering, Telecommunications and Computer Science (IEEE Cat. No.02EX542), 2002

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Research paper thumbnail of SUM IP Core Generator for Solving Task for RKHS Series Summation

2007 9th International Conference - The Experience of Designing and Applications of CAD Systems in Microelectronics, 2007

... for RKHS Series Summation Vladimir Hahanov, Svetlana Chumachenko, Dmitriy Melnik, Alina Taran... more ... for RKHS Series Summation Vladimir Hahanov, Svetlana Chumachenko, Dmitriy Melnik, Alina Taran ... [14] Chumachenko S., Kirichenko L. RKHS-Methods at Series Summation for Software implementation // International Conferences on Information Theories and Applications. ...

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Research paper thumbnail of Fault cubic simulation for digital devices

Methods and models of a digital circuit analysis for test generation and fault simulation are off... more Methods and models of a digital circuit analysis for test generation and fault simulation are offered. The two-frame cubic algebra for compact cubic coverings of sequential primitive design, faulty and fault-free simulation of digital circuits is used. Problems of digital circuits testing are formalized as linear equations. The cubic method of primitive fault simulation, which allows: to transport input fault lists to primitive outputs; to generate analytical equations for digital circuit deductive simulation of the gate, functional and algorithmic description levels.

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Research paper thumbnail of Embedded SOC F-IP diagnosis by using algebraic logical method

... functional modes (Pc): }. T,T, T,T, T,T,T,T{T , P)T(P;F)T(F RC 8 DF 7 ME 6 BS 5 AD 4 SP 3 SA ... more ... functional modes (Pc): }. T,T, T,T, T,T,T,T{T , P)T(P;F)T(F RC 8 DF 7 ME 6 BS 5 AD 4 SP 3 SA 2 PR 1 c min minn 1i i c c min minn 1i i c = ≥ ≥ = = 1) Generalized structure of Testbench synthesis [1] is represented in Fig. 2 and ...

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Research paper thumbnail of Embedded SOC F-IP diagnosis by using algebraic logical method

... functional modes (Pc): }. T,T, T,T, T,T,T,T{T , P)T(P;F)T(F RC 8 DF 7 ME 6 BS 5 AD 4 SP 3 SA ... more ... functional modes (Pc): }. T,T, T,T, T,T,T,T{T , P)T(P;F)T(F RC 8 DF 7 ME 6 BS 5 AD 4 SP 3 SA 2 PR 1 c min minn 1i i c c min minn 1i i c = ≥ ≥ = = 1) Generalized structure of Testbench synthesis [1] is represented in Fig. 2 and ...

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Research paper thumbnail of Diagnosis and repair method of SoC memory

WSEAS transactions on …, 2008

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Research paper thumbnail of Algebra-logical diagnosis model for SoC F-IP

WSEAS transactions on …, 2008

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Research paper thumbnail of ISSN 1392-1215 ELECTRONICS AND ELECTRICAL ENGINEERING. 2008. No. 5 (85)

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Test generation and fault simulation methods on the basis of cubic algebra for digital devices

Proceedings Euromicro Symposium on Digital Systems Design, 2000

ABSTRACT

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Research paper thumbnail of Optimal embedded repairing of SOC memory

ABSTRACT

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Research paper thumbnail of Fault Coverage Improving Based on Testability Analysis of the VHDL Code

2007 9th International Conference - The Experience of Designing and Applications of CAD Systems in Microelectronics, 2007

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Research paper thumbnail of Parallel Logic Simulation using Multi-Core Workstations

2007 9th International Conference - The Experience of Designing and Applications of CAD Systems in Microelectronics, 2007

Existing software in Electronic Design Automation shows lack of dual-core processors support. As ... more Existing software in Electronic Design Automation shows lack of dual-core processors support. As a result, we see bad processing resources utilization. This work is devoted to exploration of existing approaches to parallel logic and fault simulation on dual-core workstations.

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Research paper thumbnail of Structural analysis for digital devices for the simulation system

The Experience of Designing and Application of CAD Systems in Microelectronics, 2003. CADSM 2003. Proceedings of the 7th International Conference., 2003

ABSTRACT

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Research paper thumbnail of Verification Of Digital System By A New Asserting Mechanism Based On Ieee 1500 Sect Standard

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006., 2006

ABSTRACT

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Research paper thumbnail of Embedded Method of Soc Memory Repairing

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Research paper thumbnail of Embedded Method of SoC Diagnosis

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Research paper thumbnail of Algebra-logical method for SOC embedded memory repair

Algebra-logical method of optimal memory repair based on the faults covering problem solving via ... more Algebra-logical method of optimal memory repair based on the faults covering problem solving via spare components using Boolean algebra is offered. The method enables to carry out the memory repair automatically in the operating process through embedded hardware or software implementation - a service infrastructure Intellectual Property module for fault repairing.

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Research paper thumbnail of Backtraced deductive-parallel fault simulation for digital circuits

The Experience of Designing and Application of CAD Systems in Microelectronics, 2003. CADSM 2003. Proceedings of the 7th International Conference., 2003

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Research paper thumbnail of Metrics of vector logic algebra for cyber space

2010 East-West Design & Test Symposium (EWDTS), 2010

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Research paper thumbnail of Intelligent Road Control and Monitoring

Lecture Notes in Electrical Engineering, 2013

ABSTRACT

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Research paper thumbnail of Deterministic method of genetic algorithms of test generation for digital systems verification

Modern Problems of Radio Engineering, Telecommunications and Computer Science (IEEE Cat. No.02EX542), 2002

Bookmarks Related papers MentionsView impact

Research paper thumbnail of SUM IP Core Generator for Solving Task for RKHS Series Summation

2007 9th International Conference - The Experience of Designing and Applications of CAD Systems in Microelectronics, 2007

... for RKHS Series Summation Vladimir Hahanov, Svetlana Chumachenko, Dmitriy Melnik, Alina Taran... more ... for RKHS Series Summation Vladimir Hahanov, Svetlana Chumachenko, Dmitriy Melnik, Alina Taran ... [14] Chumachenko S., Kirichenko L. RKHS-Methods at Series Summation for Software implementation // International Conferences on Information Theories and Applications. ...

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