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Victor Konrad

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Papers by Victor Konrad

Research paper thumbnail of Method and apparatus for utilizing static queues in processor staging

Research paper thumbnail of Method and apparatus to reduce the size of rom used in mathematical computatiions

Research paper thumbnail of Method to reduce the power consumption of large PLAs by clock gating guided by recursive shannon decomposition of the and-plane

Research paper thumbnail of Method and mechanism for implementation-independent, on-line, end-to-end detection of faults in self-checking queues in digital hardware systems

Research paper thumbnail of On Block-Parallel Methods for Solving Linear Equations

IEEE Transactions on Computers, 1980

An MIMD-type parallel-processing system was introduced recently. Using an extended PL/I notation,... more An MIMD-type parallel-processing system was introduced recently. Using an extended PL/I notation, algorithms for the Gauss-Seidel method and for back substitution are written for this system. Block execution is shown to result in higher speedups.

Research paper thumbnail of Iterative Solution of Linear Equations on a Parallel Processor System

IEEE Transactions on Computers, 1977

Research paper thumbnail of Some “real world” problems in the analog and mixed signal domains

Designing Correct Circuits, Feb 1, 2008

DCC 08 Some" Real World" Problems in the Analog and Mixed Signal Domains Kevin D Jones ... more DCC 08 Some" Real World" Problems in the Analog and Mixed Signal Domains Kevin D Jones Jaeha Kim, Victor Konrad Slide 2 DCC 08 Abstract • Design and verification problems in the digital circuit space are well studied and there are many approaches to establishing correctness, both academic and industrial. However, the analog and mixed signal space is much less developed. • More and more systems are being designed with “mixed mode” functionality. That is to say, there are digital and analog components working ...

Research paper thumbnail of Analog property checkers: a DDR2 case study

Formal Methods in System Design, 2009

The formal specification component of verification can be exported to simulation through the idea... more The formal specification component of verification can be exported to simulation through the idea of property checkers. The essence of this approach is the automatic construction of an observer from the specification in the form of a program that can be interfaced with a simulator and alert the user if the property is violated by a simulation trace. Although not complete, this lighter approach to formal verification has been effectively used in software and digital hardware to detect errors. Recently, the idea of property checkers has been extended to analog and mixed signal systems. In this paper, we apply the property-based checking methodology to an industrial and realistic example of a DDR2 memory interface. The properties describing the DDR2 analog behavior are expressed in the formal specification language STL/PSL in form of assertions. The simulation traces generated from an actual DDR2 interface design are checked with respect to the STL/PSL assertions using the AMT tool. The focus of this paper is on the translation of the official (informal and descriptive) specification of two non-trivial DDR2 properties into STL/PSL assertions. We study both the benefits and the current limits of such approach.

Research paper thumbnail of Method and apparatus for utilizing static queues in processor staging

Research paper thumbnail of Method and apparatus to reduce the size of rom used in mathematical computatiions

Research paper thumbnail of Method to reduce the power consumption of large PLAs by clock gating guided by recursive shannon decomposition of the and-plane

Research paper thumbnail of Method and mechanism for implementation-independent, on-line, end-to-end detection of faults in self-checking queues in digital hardware systems

Research paper thumbnail of On Block-Parallel Methods for Solving Linear Equations

IEEE Transactions on Computers, 1980

An MIMD-type parallel-processing system was introduced recently. Using an extended PL/I notation,... more An MIMD-type parallel-processing system was introduced recently. Using an extended PL/I notation, algorithms for the Gauss-Seidel method and for back substitution are written for this system. Block execution is shown to result in higher speedups.

Research paper thumbnail of Iterative Solution of Linear Equations on a Parallel Processor System

IEEE Transactions on Computers, 1977

Research paper thumbnail of Some “real world” problems in the analog and mixed signal domains

Designing Correct Circuits, Feb 1, 2008

DCC 08 Some" Real World" Problems in the Analog and Mixed Signal Domains Kevin D Jones ... more DCC 08 Some" Real World" Problems in the Analog and Mixed Signal Domains Kevin D Jones Jaeha Kim, Victor Konrad Slide 2 DCC 08 Abstract • Design and verification problems in the digital circuit space are well studied and there are many approaches to establishing correctness, both academic and industrial. However, the analog and mixed signal space is much less developed. • More and more systems are being designed with “mixed mode” functionality. That is to say, there are digital and analog components working ...

Research paper thumbnail of Analog property checkers: a DDR2 case study

Formal Methods in System Design, 2009

The formal specification component of verification can be exported to simulation through the idea... more The formal specification component of verification can be exported to simulation through the idea of property checkers. The essence of this approach is the automatic construction of an observer from the specification in the form of a program that can be interfaced with a simulator and alert the user if the property is violated by a simulation trace. Although not complete, this lighter approach to formal verification has been effectively used in software and digital hardware to detect errors. Recently, the idea of property checkers has been extended to analog and mixed signal systems. In this paper, we apply the property-based checking methodology to an industrial and realistic example of a DDR2 memory interface. The properties describing the DDR2 analog behavior are expressed in the formal specification language STL/PSL in form of assertions. The simulation traces generated from an actual DDR2 interface design are checked with respect to the STL/PSL assertions using the AMT tool. The focus of this paper is on the translation of the official (informal and descriptive) specification of two non-trivial DDR2 properties into STL/PSL assertions. We study both the benefits and the current limits of such approach.

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