Venu Madhava Rao S.P. - Academia.edu (original) (raw)
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Papers by Venu Madhava Rao S.P.
In this paper we present a novel approach to analog electronic circuits fault diagnosis based on ... more In this paper we present a novel approach to analog electronic circuits fault diagnosis based on selection of both nodes and frequency for the first time as far as we know. Two fault isolation and localization algorithms are presented in this paper. The first algorithm selects nodes and frequencies which isolate all or desired number of faults. The second algorithm presented converts the fault dictionary contents into binary form. Importantly this helps in the automation of the fault diagnosis process.
International Journal of Science and Research (IJSR), 2016
Optical communication is identified as one of the advanced communications systems. Dispersion & n... more Optical communication is identified as one of the advanced communications systems. Dispersion & non-linear effects cause severe waveform distortion in single channel as well as Wavelength Division Multiplexing (WDM) systems. Of Two methods like Disperion Compensation Fiber and Optical phase compensation, Results are reported for dispersion Compensation fiber.
This paper details the design and usage for the universal asynchronous receiver/transmitter to se... more This paper details the design and usage for the universal asynchronous receiver/transmitter to serial peripheral interface .The UART-to-SPI interface can be used to communicate to SPI slave devices from a PC with a UART port. SPI is a full duplex, serial bus commonly used in the embedded world because of its simple hardware interface requirements and protocol flexibility. SPI devices are normally smaller in size (low I/O count) when compared to parallel interface devices. This design example is implemented on an ASIC device, but can easily be implemented in any of low-power field programmable gate arrays (FPGAs) to optimize system power, size,or performance requirements.
International journal on future revolution in computer science & communication engineering, Oct 31, 2017
n this paper, design of analog circuit using double gate (DG) MOSFET where the front gate output ... more n this paper, design of analog circuit using double gate (DG) MOSFET where the front gate output is changed by control voltage on the back gate. The DG devices can be used to improve the performance and reduce the power dissipation when the front gate and back gate both are independently controlled. The analysis of the analog circuits such as CMOS amplifier pair, Schmitt trigger circuit and operational trans- conductance amplifier. Transient response and output DC response of analog tunable circuits are going to be analyzed. These circuit blocks are used for low-noise, high performance integrated circuits for analog and mixed-signal applications. The design and simulation results are predicted by Microwind tool in 32nm complementary metal oxide semiconductor (CMOS) technology. KeywordsCircuits, Double Gate, Transient and output DC response
This research paper will explore the possibility of using Electroencephalographic (EEG) signals f... more This research paper will explore the possibility of using Electroencephalographic (EEG) signals for recognizing unspoken speech (trying to speak but not converted into speech ). Significant brain activations may be observed in Functional Magnetic Response Imaging (fMRI Images) & EEG signals related to speaking effort. .Brain activity patterns generated from speaking effort may be interpreted into words. .When a person tries to speak we can identify the intensities of blood flow and oxidization in brain and in those regions electrodes of EEG may be placed. From those electrical signals speaker effort will be captured and matched with library patterns. This process leads to interpretation of brain signals to words. But however we come across a basic problem that temporally correlated artifacts may interfere the signals to be recognized.
2019 1st International Conference on Innovations in Information and Communication Technology (ICIICT), 2019
In recent days the knowledge in the Brain Machine Interface is manifesting emotion recognition an... more In recent days the knowledge in the Brain Machine Interface is manifesting emotion recognition and classification. There are many studies indicating potential evidence in identifying emotions using EEG brain waves. This paper investigates and proposes a new machine learning technology in identifying the emotions through the use of latest machine learning concepts using LSTN ( Long short term memory) recurring neural networks. The acquired brain wave signals are processed for classification using discrete wavelet transform and then given to the proposed algorithm for specific emotion recognition.
INTERNATIONAL JOURNAL OF MANAGEMENT & INFORMATION TECHNOLOGY, Nov 21, 2013
The proliferation of large analog circuits and systems of ever increasing complexity has stirred ... more The proliferation of large analog circuits and systems of ever increasing complexity has stirred great interest in different methods for fault diagnosis of analog circuits. In Analog circuit fault diagnosis, the measurements of the circuit are used in the construction of the fault dictionary. The fault dictionary represents readings of the circuit under different fault conditions and one nominal condition at different test frequencies. Based on the fault dictionary readings, sets of faults which have almost the same fault signature are identified and are called ambiguity sets. In this paper the multi frequency approach to fault diagnosis has been optimized using the concept of sub-ambiguity tables. It has been shown here that the number of test frequencies required to diagnose faults has been significantly reduced and also the simulation time taken has been reduced.
International Journal of Emerging Research in Management and Technology, 2017
ault diagnosis of Analog Electronic circuits involves an exhaustive analysis of each and every co... more ault diagnosis of Analog Electronic circuits involves an exhaustive analysis of each and every component of the circuit. This is a procedure which is an analysis of each and every component and the complexity increases as the number of components increase. The faults in different components have varied effects on the performance of the circuit and some of the components are more critical than others. In this paper a method has been proposed to identify the critical components in an Analog circuit being diagnosed for faults. Sensitivity Analysis is used to identify these critical components. A second order Butterworth Filter is used to illustrate the method proposed in this paper. In this paper an algorithm has been proposed which identifies the most critical component of the circuit.
As the process technology is becoming less than 32nm, the variations in Gate length, Channel widt... more As the process technology is becoming less than 32nm, the variations in Gate length, Channel width and Gate Oxide thickness affect the charge and potential distributions. These variations in turn will affect the Voltage-Current characteristics of the device. Nano wire FET devices are promising candidates to realize the high speed operation of the FET. However high access resistance, capacitances and self heating effects are challenges are for multi Gate FET architectures. Also the analysis of their behavior is complex because it is influenced by the size, shape, channel orientation and strain induced by the fabrication process. The charge distributions are to be analyzed with respect to Azimuthal coordinates in weak inversion region which is affected by the charge distribution. In this paper the I-V characteristics of the GAA Nano Wire FET are optimized using Taguchi method.
Procedia Materials Science, 2015
The advent of new nanometer process technologies has made it possible to integrate billions of tr... more The advent of new nanometer process technologies has made it possible to integrate billions of transistors on a single chip. The increase in functionality coupled with decrease in size has resulted in more power consumption and this increases the need for a better and efficient power dissipation. This is resulting in significant amount of leakage currents flowing into the substrate made up of Silicon. This is resulting in increase in substrate heating and the thermal noise thus generated is coupling with the other signals. In this paper optimization of the Sherwood parameter has been carried and its effect on controlling the substrate heating is studied.
Procedia Materials Science, 2015
With advent of nano technology, a threshold voltage of a MOSFET can be engineered. In order to in... more With advent of nano technology, a threshold voltage of a MOSFET can be engineered. In order to increase the packing density of the transistors on multicore processor/ SOC with FPGA and processor, and 3-D IC realization, stacking of materials are necessary with lesser parasites like capacitance, voltage drop etc. In this paper, we present Silicon as a base material and metal like TiN (Titanium Nitride) as top layer is analyzed. The parameters of the different stacked materials are optimized to achieve required C Stack (Stack Capacitance) and V Th. It is used explore the behavior of dual oxide MOS parameters like oxide material, electron affinity, bandgap, dielectric constant, and thickness.
Procedia Materials Science, 2015
Journal of Circuits, …, 2008
An efficient method to eliminate redundant frequencies present in one of the existing multi-frequ... more An efficient method to eliminate redundant frequencies present in one of the existing multi-frequency methods for analog fault diagnosis is proposed in this paper. First the two-dimensional fault dictionary is constructed where entries are gain signatures of all faults and frequencies. The faults belonging to the same quantization levels are numbered sequentially and a frequency that has an ambiguity set with the highest number faults is eliminated after verifying that there are no repetitions after the deletion of this frequency. In this manner, all frequencies are examined for deletion. Finally the test frequencies, which cannot be deleted, remain resulting in a minimal set of test frequencies of a network to isolate a given set of faults. Another method proposes a technique, which generates more number of frequencies to isolate all the faults, if the test frequencies generated using the existing methods are not sufficient.
In this paper we present a novel approach to analog electronic circuits fault diagnosis based on ... more In this paper we present a novel approach to analog electronic circuits fault diagnosis based on selection of both nodes and frequency for the first time as far as we know. Two fault isolation and localization algorithms are presented in this paper. The first algorithm selects nodes and frequencies which isolate all or desired number of faults. The second algorithm presented converts the fault dictionary contents into binary form. Importantly this helps in the automation of the fault diagnosis process.
International Journal of Science and Research (IJSR), 2016
Optical communication is identified as one of the advanced communications systems. Dispersion & n... more Optical communication is identified as one of the advanced communications systems. Dispersion & non-linear effects cause severe waveform distortion in single channel as well as Wavelength Division Multiplexing (WDM) systems. Of Two methods like Disperion Compensation Fiber and Optical phase compensation, Results are reported for dispersion Compensation fiber.
This paper details the design and usage for the universal asynchronous receiver/transmitter to se... more This paper details the design and usage for the universal asynchronous receiver/transmitter to serial peripheral interface .The UART-to-SPI interface can be used to communicate to SPI slave devices from a PC with a UART port. SPI is a full duplex, serial bus commonly used in the embedded world because of its simple hardware interface requirements and protocol flexibility. SPI devices are normally smaller in size (low I/O count) when compared to parallel interface devices. This design example is implemented on an ASIC device, but can easily be implemented in any of low-power field programmable gate arrays (FPGAs) to optimize system power, size,or performance requirements.
International journal on future revolution in computer science & communication engineering, Oct 31, 2017
n this paper, design of analog circuit using double gate (DG) MOSFET where the front gate output ... more n this paper, design of analog circuit using double gate (DG) MOSFET where the front gate output is changed by control voltage on the back gate. The DG devices can be used to improve the performance and reduce the power dissipation when the front gate and back gate both are independently controlled. The analysis of the analog circuits such as CMOS amplifier pair, Schmitt trigger circuit and operational trans- conductance amplifier. Transient response and output DC response of analog tunable circuits are going to be analyzed. These circuit blocks are used for low-noise, high performance integrated circuits for analog and mixed-signal applications. The design and simulation results are predicted by Microwind tool in 32nm complementary metal oxide semiconductor (CMOS) technology. KeywordsCircuits, Double Gate, Transient and output DC response
This research paper will explore the possibility of using Electroencephalographic (EEG) signals f... more This research paper will explore the possibility of using Electroencephalographic (EEG) signals for recognizing unspoken speech (trying to speak but not converted into speech ). Significant brain activations may be observed in Functional Magnetic Response Imaging (fMRI Images) & EEG signals related to speaking effort. .Brain activity patterns generated from speaking effort may be interpreted into words. .When a person tries to speak we can identify the intensities of blood flow and oxidization in brain and in those regions electrodes of EEG may be placed. From those electrical signals speaker effort will be captured and matched with library patterns. This process leads to interpretation of brain signals to words. But however we come across a basic problem that temporally correlated artifacts may interfere the signals to be recognized.
2019 1st International Conference on Innovations in Information and Communication Technology (ICIICT), 2019
In recent days the knowledge in the Brain Machine Interface is manifesting emotion recognition an... more In recent days the knowledge in the Brain Machine Interface is manifesting emotion recognition and classification. There are many studies indicating potential evidence in identifying emotions using EEG brain waves. This paper investigates and proposes a new machine learning technology in identifying the emotions through the use of latest machine learning concepts using LSTN ( Long short term memory) recurring neural networks. The acquired brain wave signals are processed for classification using discrete wavelet transform and then given to the proposed algorithm for specific emotion recognition.
INTERNATIONAL JOURNAL OF MANAGEMENT & INFORMATION TECHNOLOGY, Nov 21, 2013
The proliferation of large analog circuits and systems of ever increasing complexity has stirred ... more The proliferation of large analog circuits and systems of ever increasing complexity has stirred great interest in different methods for fault diagnosis of analog circuits. In Analog circuit fault diagnosis, the measurements of the circuit are used in the construction of the fault dictionary. The fault dictionary represents readings of the circuit under different fault conditions and one nominal condition at different test frequencies. Based on the fault dictionary readings, sets of faults which have almost the same fault signature are identified and are called ambiguity sets. In this paper the multi frequency approach to fault diagnosis has been optimized using the concept of sub-ambiguity tables. It has been shown here that the number of test frequencies required to diagnose faults has been significantly reduced and also the simulation time taken has been reduced.
International Journal of Emerging Research in Management and Technology, 2017
ault diagnosis of Analog Electronic circuits involves an exhaustive analysis of each and every co... more ault diagnosis of Analog Electronic circuits involves an exhaustive analysis of each and every component of the circuit. This is a procedure which is an analysis of each and every component and the complexity increases as the number of components increase. The faults in different components have varied effects on the performance of the circuit and some of the components are more critical than others. In this paper a method has been proposed to identify the critical components in an Analog circuit being diagnosed for faults. Sensitivity Analysis is used to identify these critical components. A second order Butterworth Filter is used to illustrate the method proposed in this paper. In this paper an algorithm has been proposed which identifies the most critical component of the circuit.
As the process technology is becoming less than 32nm, the variations in Gate length, Channel widt... more As the process technology is becoming less than 32nm, the variations in Gate length, Channel width and Gate Oxide thickness affect the charge and potential distributions. These variations in turn will affect the Voltage-Current characteristics of the device. Nano wire FET devices are promising candidates to realize the high speed operation of the FET. However high access resistance, capacitances and self heating effects are challenges are for multi Gate FET architectures. Also the analysis of their behavior is complex because it is influenced by the size, shape, channel orientation and strain induced by the fabrication process. The charge distributions are to be analyzed with respect to Azimuthal coordinates in weak inversion region which is affected by the charge distribution. In this paper the I-V characteristics of the GAA Nano Wire FET are optimized using Taguchi method.
Procedia Materials Science, 2015
The advent of new nanometer process technologies has made it possible to integrate billions of tr... more The advent of new nanometer process technologies has made it possible to integrate billions of transistors on a single chip. The increase in functionality coupled with decrease in size has resulted in more power consumption and this increases the need for a better and efficient power dissipation. This is resulting in significant amount of leakage currents flowing into the substrate made up of Silicon. This is resulting in increase in substrate heating and the thermal noise thus generated is coupling with the other signals. In this paper optimization of the Sherwood parameter has been carried and its effect on controlling the substrate heating is studied.
Procedia Materials Science, 2015
With advent of nano technology, a threshold voltage of a MOSFET can be engineered. In order to in... more With advent of nano technology, a threshold voltage of a MOSFET can be engineered. In order to increase the packing density of the transistors on multicore processor/ SOC with FPGA and processor, and 3-D IC realization, stacking of materials are necessary with lesser parasites like capacitance, voltage drop etc. In this paper, we present Silicon as a base material and metal like TiN (Titanium Nitride) as top layer is analyzed. The parameters of the different stacked materials are optimized to achieve required C Stack (Stack Capacitance) and V Th. It is used explore the behavior of dual oxide MOS parameters like oxide material, electron affinity, bandgap, dielectric constant, and thickness.
Procedia Materials Science, 2015
Journal of Circuits, …, 2008
An efficient method to eliminate redundant frequencies present in one of the existing multi-frequ... more An efficient method to eliminate redundant frequencies present in one of the existing multi-frequency methods for analog fault diagnosis is proposed in this paper. First the two-dimensional fault dictionary is constructed where entries are gain signatures of all faults and frequencies. The faults belonging to the same quantization levels are numbered sequentially and a frequency that has an ambiguity set with the highest number faults is eliminated after verifying that there are no repetitions after the deletion of this frequency. In this manner, all frequencies are examined for deletion. Finally the test frequencies, which cannot be deleted, remain resulting in a minimal set of test frequencies of a network to isolate a given set of faults. Another method proposes a technique, which generates more number of frequencies to isolate all the faults, if the test frequencies generated using the existing methods are not sufficient.