Vijaya Lakshmi - Academia.edu (original) (raw)
Uploads
Papers by Vijaya Lakshmi
We propose a new sequential multiplier design that generates the radix-16 partial products (e.g.,... more We propose a new sequential multiplier design that generates the radix-16 partial products (e.g., ) as two high ( ) and low ( ) components, such that = 4 + , , ∈ {0, 1, 2, 3} × , where denotes the multiplicand. The required hard 3 multiple is generated in a preliminary cycle to the advantage of reducing the cycle time of the main iteration. Two radix-16 carry-save adders are used to generate the radix-16 accumulated partial product. The synthesis results show improved latency, power dissipation, and energy consumption over the previous relevant designs at the cost of additional silicon area, while however, the energy-area product is also lowered.
We propose a new sequential multiplier design that generates the radix-16 partial products (e.g.,... more We propose a new sequential multiplier design that generates the radix-16 partial products (e.g., ) as two high ( ) and low ( ) components, such that = 4 + , , ∈ {0, 1, 2, 3} × , where denotes the multiplicand. The required hard 3 multiple is generated in a preliminary cycle to the advantage of reducing the cycle time of the main iteration. Two radix-16 carry-save adders are used to generate the radix-16 accumulated partial product. The synthesis results show improved latency, power dissipation, and energy consumption over the previous relevant designs at the cost of additional silicon area, while however, the energy-area product is also lowered.