Yao-wen Chang - Academia.edu (original) (raw)
Papers by Yao-wen Chang
2007 IEEE/ACM International Conference on Computer-Aided Design, 2007
ABSTRACT
Proceedings of the 1998 international symposium on Physical design - ISPD '98, 1998
ABSTRACT An FPD switch module M with w terminals on each side is said to be universal if every se... more ABSTRACT An FPD switch module M with w terminals on each side is said to be universal if every set of nets satisfying the dimensional constraint (i.e., the number of nets on each side of M is at most w) is simultaneously routable through M [8]. Chang, Wong, and Wong have identified a class of universal switch blocks in [8]. In this paper, we consider the design and routing problems for another popular model of switch modules called switch matrices. Unlike switch blocks, we prove that there exist no universal switch matrices. Nevertheless, we present quasi-universal switch matrices which have the maximum possible routing capacities among all switch matrices of the same size, and show that their routing capacities converge to those of universal switch blocks. Each of the quasi-universal switch matrices of size w has a total of only 14w Gamma 20 (14w Gamma 21) switches if w is even (odd), w ? 1, compared to a fully populated one which has 3w 2 Gamma 2w switches. We prove that no switch matrix...
Proceedings of the 2004 international symposium on Physical design - ISPD '04, 2004
As technology advances into nanometer territory, the antenna problem has caused significant impac... more As technology advances into nanometer territory, the antenna problem has caused significant impact on routing tools. The antenna effect is a phenomenon of plasmainduced gate oxide degradation caused by charge accumulation on conductors.
2006 IEEE/ACM International Conference on Computer Aided Design, 2006
ABSTRACT
Proceedings 2000 International Conference on Computer Design, 2000
ABSTRACT
2009 Asia and South Pacific Design Automation Conference, 2009
Global routing is an important step for physical design. In this paper, we develop a new global r... more Global routing is an important step for physical design. In this paper, we develop a new global router, NTUgr, that contains three major steps: prerouting, initial routing, and enhanced iterative negotiation-based rip-up/rerouting (INR). The prerouting employs a two-stage technique of congestion-hotspot historical cost pre-increment followed by small bounding-box area routing. The initial routing is based on efficient iterative monotonic routing. For traditional INR, it has evolved as the main stream for the state-of-the-art global routers, which reveals its great ability to reduce the congestion and overflow. As pointed out by recent works, however, traditional INR may get stuck at local optima as the number of iterations increases. To remedy this deficiency, we replace INR by enhanced iterative forbidden-region rip-up/rerouting (IFR) which features three new techniques of (1) multiple forbidden regions expansion, (2) critical subnet rerouting selection, and (3) look-ahead historical cost increment. Experimental results show that NTUgr achieves highquality results for the ISPD'07 and ISPD'08 benchmarks for both overflow and runtime.
2008 IEEE/ACM International Conference on Computer-Aided Design, 2008
Global routing for modern large-scale circuit designs has attracted much attention in the recent ... more Global routing for modern large-scale circuit designs has attracted much attention in the recent literature. Most of the state-of-the-art academic global routers just work on a simplified routing congestion model that ignores the essential via capacity for routing through multiple metal layers. Such a simplified model would easily cause fatal routability problems in subsequent detailed routing. To remedy this deficiency, we present in this paper a more effective congestion metric that considers both the in-tile nets and the residual via capacity for global routing. With this congestion metric, we develop a new global router that features two novel routing algorithms for congestion optimization, namely least-flexibility-first routing and multi-source multi-sink escaping-point routing. The least-flexibility-first routing processes the nets with the least flexibility first, facilitating a quick prediction of congestion hot spots for the subsequent nets. Enjoying lower time complexity than traditional maze and A*-search routing, in particular, the linear-time escaping-point routing guarantees to find the optimal solution and achieves the theoretical lower-bound time complexity. Experimental results show that our global router can achieve very high-quality routing solutions with more reasonable via usage, which can benefit and correctly guide subsequent detailed routing.
Proceedings of the 49th Annual Design Automation Conference on - DAC '12, 2012
ABSTRACT In today's IC production, the design processes of chips, packages, and boards ar... more ABSTRACT In today's IC production, the design processes of chips, packages, and boards are typically separate from each other. The lack of information from other domains causes significant design convergence problems and greatly reduces design quality. In this paper, we propose the first chip-package-board code-sign methodology that provides true bi-directional information interactions among the three design domains. The code-sign adopts a two-pass flow of board-package-chip followed by chip-package-board routing interactions to facilitate the overall design integration. Experimental results show that our code-sign flow succeeds in the routing for all test cases, while a traditional flow and two board-driven flows fail all cases.
Asia and South Pacific Conference on Design Automation, 2006., 2006
The flip-chip package gives the highest chip density of any packaging method to support the pad-l... more The flip-chip package gives the highest chip density of any packaging method to support the pad-limited ASIC design. One of the most important characteristics of flip-chip designs is that the input/output buffers could be placed anywhere inside a chip. In this paper, we first introduce the floorplan- ning problem for the flip-chip design and formulate it as assigning the posi-
IEEE Electron Device Letters, 2004
The temperature effect on the read current of a two-bit nitride-storage Flash memory cell is inve... more The temperature effect on the read current of a two-bit nitride-storage Flash memory cell is investigated. In contrast to a conventional silicon-oxide-nitride-oxide (SONOS) cell with uniform Fowler-Nordheim (FN) programming, a significant high-state read current increase, which results in the read window narrowing at high temperature, is observed in a channel hot electron (CHE) programmed cell. The increment of high-state leakage current shows a positive correlation with program/erase threshold voltage window. Since the temperature effect is very sensitive to a locally trapped charge profile, a two-dimensional simulation with a step charge profile is employed to characterize the relationship between current increment and both charge width and charge density.
2007 IEEE/ACM International Conference on Computer-Aided Design, 2007
We introduce in this paper a new problem of post-mask engineering change order (ECO) timing optim... more We introduce in this paper a new problem of post-mask engineering change order (ECO) timing optimization using spare-cell rewiring and present a two-phase framework for this problem. Spare-cell rewiring is a popular technique for incremental timing optimization and/or functional change after the placement stage. The spare-cell rewiring problem is very challenging because of its dynamic wiring cost nature for selecting a spare cell, while the existing related problems consider only static wiring cost: once a standard cell is placed, its physical location is fixed and so is its wiring cost. For the sparecell rewiring problem, each rewiring could make some spare cells become ordinary standard cells and some standard cells become new spare cells simultaneously. As a result, the wiring cost becomes dynamic and further complicates the optimization process. For the addressed problem, we present a two-phase framework of 1) buffer insertion and gate sizing followed by 2) technology remapping. For Phase 1, we present a dynamic programming algorithm considering the dynamic cost, called dynamic cost programming, for the ECO timing optimization with spare cells. Without loss of solution optimality, we further present an effective pruning method by selecting spare cells only inside an essential bounding polygon to reduce the solution space. For those ECO timing paths that cannot be fixed during Phase 1, we apply technology remapping on the spare cells to restructure the circuit to fix the timing violations. The whole framework is integrated into a commercial design flow. Experimental results based on five industry benchmarks show that our method is very effective and efficient in fixing the timing violations of ECO paths.
IEEE/ACM International Conference on Computer-Aided Design, 1984
As in traditional ASIC technologies, FPGA routing usually consists of two steps: global routing a... more As in traditional ASIC technologies, FPGA routing usually consists of two steps: global routing and detailed routing. Unlike existing FPGA detailed routers, which can take full advantage of the special structures of the programmable routing resources, FPGA global routing algorithms still greatly resemble their counterparts in the traditional ASIC technologies. In particular, the routing congestion information of a switch block
2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2011
To accommodate the ever-growing pin number of complex PCB designs, the staggered pin array is int... more To accommodate the ever-growing pin number of complex PCB designs, the staggered pin array is introduced for modern designs with higher pin density. However, the escape routing for staggered pin arrays, which is a key component of PCB routing, is significantly different from that for grid arrays. This paper presents a routing algorithm for the escape routing for staggered-pin-array PCBs. We first analyze the properties of staggered pin arrays, and propose an orthogonal-side wiring style that fully utilizes the routing resource of the staggered pin array. An LP/ILP based algorithm is presented to solve the staggeredpin-array escape routing problem. Experimental results show that our approach successfully completed the routing for all testcases efficiently and effectively.
2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2010
ABSTRACT The double patterning technology (DPT), in which a dense layout pattern is decomposed in... more ABSTRACT The double patterning technology (DPT), in which a dense layout pattern is decomposed into two separate masks to relax its pitch, is the most popular lithography solution for the sub-22nm node to enhance pattern printability. Previous works focus on stitch insertion to improve the decomposition success rate. However, there exist native conflicts (NC's) which cannot be resolved by any kind of stitch insertion. A design with NC's is not DPT-compliance and will eventually fail the decomposition, resulting in DFM redesign and longer design cycles. In this paper, we give a sufficient condition for the NC existence and propose a geometry-based method for NC prediction to develop an early stage analyzer for DPT decomposability checking. Then, a wire perturbation algorithm is presented to fix as many NC's in the layout as possible. The algorithm is based on iterative 1D-compaction and can easily be embedded into existing industrial compaction systems. Experimental results show that the proposed algorithm can significantly reduce the number of NC's by an average of 85%, which can effectively increase the decomposition success rate for the next stage.
Proceedings 2000 International Conference on Computer Design, 2000
ABSTRACT Due to the layout complexity in deep sub-micron technology, integrated circuit blocks ar... more ABSTRACT Due to the layout complexity in deep sub-micron technology, integrated circuit blocks are often not rectangular. However, literature on general rectilinear block placement is still quite limited. In this paper, we present approaches for handling the placement for arbitrarily shaped rectilinear blocks, based on a newly developed data structure called B*-trees [1]. Experimental results show that our algorithm achieves optimal or near optimal block placement for benchmarks with multiple shaped blocks. 1
Handbook of Algorithms for Physical Design Automation, 2008
Essential Issues in SOC Design, 2007
Handbook of Algorithms for Physical Design Automation, 2008
2006 IEEE/ACM International Conference on Computer Aided Design, 2006
Power consumption is a crucial concern in nanometer chip design. Researchers have shown that mult... more Power consumption is a crucial concern in nanometer chip design. Researchers have shown that multiple supply voltage (MSV) is an effective method for power consumption reduction. The underlying idea behind MSV is the trade-off between power saving and performance. In this paper, we present an effective voltage assignment technique based on dynamic programming. Given a netlist without reconvergent fanouts, the dynamic programming can guarantee an optimal solution for the voltage assignment. We then generate a level shifter for each net that connects two blocks in different voltage domains, and perform power-network aware floorplanning for the MSV design. Experimental results show that our floorplanner is very effective in optimizing power consumption under timing constraints.
IEEE International SOC Conference, 2004. Proceedings., 2004
As technology advances into nanometer territory, the antenna problem has caused significant impac... more As technology advances into nanometer territory, the antenna problem has caused significant impact on routing tools. The antenna effect is a phenomenon of plasma-induced gate oxide degradation caused by charge accumulation on conductors. It directly influences reliability, manufacturability and yield of VLSI circuits, especially in deep-submicron technology using high-density plasma. Furthermore, the continuous increase of the problem size of IC routing is also a great challenge to existing routing algorithms. In this paper, we propose a novel framework for multilevel full-chip routing with antenna avoidance using built-in jumper insertion approach. Compared with the state-of-the-art multilevel routing, the experimental results show that our approach reduced 100% antenna-violated gates and results in fewer wirelength, vias, and delay increase. r fabrication technologies, manufacturing yield and product reliability is becoming one of the most important issues among the other existing ones, such as small die size, high speed, low power and so on [1]. The fine feature size of modern IC technologies is typically achieved by using plasmabased processes. As the technology enters the deep-submicron era, more stringent process requirements cause some advanced high-density plasma reactors adopted in the production lines to achieve fine-line patterns . However, these plasma-based processes have a tendency to charge conducting components of a fabricated structure. The existing experimental evidence indicates that charging may affect the quality of the thin oxide. This is called the antenna effect (also called ''plasma-induced gate-oxide damage''). During metallization, chips are usually processed ''from the bulk up'', each time adding an additional layer of interconnect. While the metal interconnect chip is being assembled, the interconnect of a net will consist of a number of disconnected pieces of floating metal. Long floating interconnects act as temporary capacitors to store charges gained from the energy provided during fabrication steps such as chemical mechanical polishing (CMP). A random discharge of the floating node due to subsequent process steps could permanently damage transistors, rendering the IC useless .
2007 IEEE/ACM International Conference on Computer-Aided Design, 2007
ABSTRACT
Proceedings of the 1998 international symposium on Physical design - ISPD '98, 1998
ABSTRACT An FPD switch module M with w terminals on each side is said to be universal if every se... more ABSTRACT An FPD switch module M with w terminals on each side is said to be universal if every set of nets satisfying the dimensional constraint (i.e., the number of nets on each side of M is at most w) is simultaneously routable through M [8]. Chang, Wong, and Wong have identified a class of universal switch blocks in [8]. In this paper, we consider the design and routing problems for another popular model of switch modules called switch matrices. Unlike switch blocks, we prove that there exist no universal switch matrices. Nevertheless, we present quasi-universal switch matrices which have the maximum possible routing capacities among all switch matrices of the same size, and show that their routing capacities converge to those of universal switch blocks. Each of the quasi-universal switch matrices of size w has a total of only 14w Gamma 20 (14w Gamma 21) switches if w is even (odd), w ? 1, compared to a fully populated one which has 3w 2 Gamma 2w switches. We prove that no switch matrix...
Proceedings of the 2004 international symposium on Physical design - ISPD '04, 2004
As technology advances into nanometer territory, the antenna problem has caused significant impac... more As technology advances into nanometer territory, the antenna problem has caused significant impact on routing tools. The antenna effect is a phenomenon of plasmainduced gate oxide degradation caused by charge accumulation on conductors.
2006 IEEE/ACM International Conference on Computer Aided Design, 2006
ABSTRACT
Proceedings 2000 International Conference on Computer Design, 2000
ABSTRACT
2009 Asia and South Pacific Design Automation Conference, 2009
Global routing is an important step for physical design. In this paper, we develop a new global r... more Global routing is an important step for physical design. In this paper, we develop a new global router, NTUgr, that contains three major steps: prerouting, initial routing, and enhanced iterative negotiation-based rip-up/rerouting (INR). The prerouting employs a two-stage technique of congestion-hotspot historical cost pre-increment followed by small bounding-box area routing. The initial routing is based on efficient iterative monotonic routing. For traditional INR, it has evolved as the main stream for the state-of-the-art global routers, which reveals its great ability to reduce the congestion and overflow. As pointed out by recent works, however, traditional INR may get stuck at local optima as the number of iterations increases. To remedy this deficiency, we replace INR by enhanced iterative forbidden-region rip-up/rerouting (IFR) which features three new techniques of (1) multiple forbidden regions expansion, (2) critical subnet rerouting selection, and (3) look-ahead historical cost increment. Experimental results show that NTUgr achieves highquality results for the ISPD'07 and ISPD'08 benchmarks for both overflow and runtime.
2008 IEEE/ACM International Conference on Computer-Aided Design, 2008
Global routing for modern large-scale circuit designs has attracted much attention in the recent ... more Global routing for modern large-scale circuit designs has attracted much attention in the recent literature. Most of the state-of-the-art academic global routers just work on a simplified routing congestion model that ignores the essential via capacity for routing through multiple metal layers. Such a simplified model would easily cause fatal routability problems in subsequent detailed routing. To remedy this deficiency, we present in this paper a more effective congestion metric that considers both the in-tile nets and the residual via capacity for global routing. With this congestion metric, we develop a new global router that features two novel routing algorithms for congestion optimization, namely least-flexibility-first routing and multi-source multi-sink escaping-point routing. The least-flexibility-first routing processes the nets with the least flexibility first, facilitating a quick prediction of congestion hot spots for the subsequent nets. Enjoying lower time complexity than traditional maze and A*-search routing, in particular, the linear-time escaping-point routing guarantees to find the optimal solution and achieves the theoretical lower-bound time complexity. Experimental results show that our global router can achieve very high-quality routing solutions with more reasonable via usage, which can benefit and correctly guide subsequent detailed routing.
Proceedings of the 49th Annual Design Automation Conference on - DAC '12, 2012
ABSTRACT In today's IC production, the design processes of chips, packages, and boards ar... more ABSTRACT In today's IC production, the design processes of chips, packages, and boards are typically separate from each other. The lack of information from other domains causes significant design convergence problems and greatly reduces design quality. In this paper, we propose the first chip-package-board code-sign methodology that provides true bi-directional information interactions among the three design domains. The code-sign adopts a two-pass flow of board-package-chip followed by chip-package-board routing interactions to facilitate the overall design integration. Experimental results show that our code-sign flow succeeds in the routing for all test cases, while a traditional flow and two board-driven flows fail all cases.
Asia and South Pacific Conference on Design Automation, 2006., 2006
The flip-chip package gives the highest chip density of any packaging method to support the pad-l... more The flip-chip package gives the highest chip density of any packaging method to support the pad-limited ASIC design. One of the most important characteristics of flip-chip designs is that the input/output buffers could be placed anywhere inside a chip. In this paper, we first introduce the floorplan- ning problem for the flip-chip design and formulate it as assigning the posi-
IEEE Electron Device Letters, 2004
The temperature effect on the read current of a two-bit nitride-storage Flash memory cell is inve... more The temperature effect on the read current of a two-bit nitride-storage Flash memory cell is investigated. In contrast to a conventional silicon-oxide-nitride-oxide (SONOS) cell with uniform Fowler-Nordheim (FN) programming, a significant high-state read current increase, which results in the read window narrowing at high temperature, is observed in a channel hot electron (CHE) programmed cell. The increment of high-state leakage current shows a positive correlation with program/erase threshold voltage window. Since the temperature effect is very sensitive to a locally trapped charge profile, a two-dimensional simulation with a step charge profile is employed to characterize the relationship between current increment and both charge width and charge density.
2007 IEEE/ACM International Conference on Computer-Aided Design, 2007
We introduce in this paper a new problem of post-mask engineering change order (ECO) timing optim... more We introduce in this paper a new problem of post-mask engineering change order (ECO) timing optimization using spare-cell rewiring and present a two-phase framework for this problem. Spare-cell rewiring is a popular technique for incremental timing optimization and/or functional change after the placement stage. The spare-cell rewiring problem is very challenging because of its dynamic wiring cost nature for selecting a spare cell, while the existing related problems consider only static wiring cost: once a standard cell is placed, its physical location is fixed and so is its wiring cost. For the sparecell rewiring problem, each rewiring could make some spare cells become ordinary standard cells and some standard cells become new spare cells simultaneously. As a result, the wiring cost becomes dynamic and further complicates the optimization process. For the addressed problem, we present a two-phase framework of 1) buffer insertion and gate sizing followed by 2) technology remapping. For Phase 1, we present a dynamic programming algorithm considering the dynamic cost, called dynamic cost programming, for the ECO timing optimization with spare cells. Without loss of solution optimality, we further present an effective pruning method by selecting spare cells only inside an essential bounding polygon to reduce the solution space. For those ECO timing paths that cannot be fixed during Phase 1, we apply technology remapping on the spare cells to restructure the circuit to fix the timing violations. The whole framework is integrated into a commercial design flow. Experimental results based on five industry benchmarks show that our method is very effective and efficient in fixing the timing violations of ECO paths.
IEEE/ACM International Conference on Computer-Aided Design, 1984
As in traditional ASIC technologies, FPGA routing usually consists of two steps: global routing a... more As in traditional ASIC technologies, FPGA routing usually consists of two steps: global routing and detailed routing. Unlike existing FPGA detailed routers, which can take full advantage of the special structures of the programmable routing resources, FPGA global routing algorithms still greatly resemble their counterparts in the traditional ASIC technologies. In particular, the routing congestion information of a switch block
2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2011
To accommodate the ever-growing pin number of complex PCB designs, the staggered pin array is int... more To accommodate the ever-growing pin number of complex PCB designs, the staggered pin array is introduced for modern designs with higher pin density. However, the escape routing for staggered pin arrays, which is a key component of PCB routing, is significantly different from that for grid arrays. This paper presents a routing algorithm for the escape routing for staggered-pin-array PCBs. We first analyze the properties of staggered pin arrays, and propose an orthogonal-side wiring style that fully utilizes the routing resource of the staggered pin array. An LP/ILP based algorithm is presented to solve the staggeredpin-array escape routing problem. Experimental results show that our approach successfully completed the routing for all testcases efficiently and effectively.
2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2010
ABSTRACT The double patterning technology (DPT), in which a dense layout pattern is decomposed in... more ABSTRACT The double patterning technology (DPT), in which a dense layout pattern is decomposed into two separate masks to relax its pitch, is the most popular lithography solution for the sub-22nm node to enhance pattern printability. Previous works focus on stitch insertion to improve the decomposition success rate. However, there exist native conflicts (NC's) which cannot be resolved by any kind of stitch insertion. A design with NC's is not DPT-compliance and will eventually fail the decomposition, resulting in DFM redesign and longer design cycles. In this paper, we give a sufficient condition for the NC existence and propose a geometry-based method for NC prediction to develop an early stage analyzer for DPT decomposability checking. Then, a wire perturbation algorithm is presented to fix as many NC's in the layout as possible. The algorithm is based on iterative 1D-compaction and can easily be embedded into existing industrial compaction systems. Experimental results show that the proposed algorithm can significantly reduce the number of NC's by an average of 85%, which can effectively increase the decomposition success rate for the next stage.
Proceedings 2000 International Conference on Computer Design, 2000
ABSTRACT Due to the layout complexity in deep sub-micron technology, integrated circuit blocks ar... more ABSTRACT Due to the layout complexity in deep sub-micron technology, integrated circuit blocks are often not rectangular. However, literature on general rectilinear block placement is still quite limited. In this paper, we present approaches for handling the placement for arbitrarily shaped rectilinear blocks, based on a newly developed data structure called B*-trees [1]. Experimental results show that our algorithm achieves optimal or near optimal block placement for benchmarks with multiple shaped blocks. 1
Handbook of Algorithms for Physical Design Automation, 2008
Essential Issues in SOC Design, 2007
Handbook of Algorithms for Physical Design Automation, 2008
2006 IEEE/ACM International Conference on Computer Aided Design, 2006
Power consumption is a crucial concern in nanometer chip design. Researchers have shown that mult... more Power consumption is a crucial concern in nanometer chip design. Researchers have shown that multiple supply voltage (MSV) is an effective method for power consumption reduction. The underlying idea behind MSV is the trade-off between power saving and performance. In this paper, we present an effective voltage assignment technique based on dynamic programming. Given a netlist without reconvergent fanouts, the dynamic programming can guarantee an optimal solution for the voltage assignment. We then generate a level shifter for each net that connects two blocks in different voltage domains, and perform power-network aware floorplanning for the MSV design. Experimental results show that our floorplanner is very effective in optimizing power consumption under timing constraints.
IEEE International SOC Conference, 2004. Proceedings., 2004
As technology advances into nanometer territory, the antenna problem has caused significant impac... more As technology advances into nanometer territory, the antenna problem has caused significant impact on routing tools. The antenna effect is a phenomenon of plasma-induced gate oxide degradation caused by charge accumulation on conductors. It directly influences reliability, manufacturability and yield of VLSI circuits, especially in deep-submicron technology using high-density plasma. Furthermore, the continuous increase of the problem size of IC routing is also a great challenge to existing routing algorithms. In this paper, we propose a novel framework for multilevel full-chip routing with antenna avoidance using built-in jumper insertion approach. Compared with the state-of-the-art multilevel routing, the experimental results show that our approach reduced 100% antenna-violated gates and results in fewer wirelength, vias, and delay increase. r fabrication technologies, manufacturing yield and product reliability is becoming one of the most important issues among the other existing ones, such as small die size, high speed, low power and so on [1]. The fine feature size of modern IC technologies is typically achieved by using plasmabased processes. As the technology enters the deep-submicron era, more stringent process requirements cause some advanced high-density plasma reactors adopted in the production lines to achieve fine-line patterns . However, these plasma-based processes have a tendency to charge conducting components of a fabricated structure. The existing experimental evidence indicates that charging may affect the quality of the thin oxide. This is called the antenna effect (also called ''plasma-induced gate-oxide damage''). During metallization, chips are usually processed ''from the bulk up'', each time adding an additional layer of interconnect. While the metal interconnect chip is being assembled, the interconnect of a net will consist of a number of disconnected pieces of floating metal. Long floating interconnects act as temporary capacitors to store charges gained from the energy provided during fabrication steps such as chemical mechanical polishing (CMP). A random discharge of the floating node due to subsequent process steps could permanently damage transistors, rendering the IC useless .