Yeon Chang Hahm - Academia.edu (original) (raw)

Papers by Yeon Chang Hahm

The development of pover electronic devices and various microprocessor control techniques have be... more The development of pover electronic devices and various microprocessor control techniques have been surmounting the critical point of the nonlinear characteristics in electric machine drives, and the results made more use of the AC motor system. But, veil known technique to drive AC machine in recent days, SPWM inverter-fed induction machine produces mechanically and electrically generated unpleasant audible noise.

Design of PCB interconnects for data channels running at bitrate 50 Gbps and beyond is a very cha... more Design of PCB interconnects for data channels running at bitrate 50 Gbps and beyond is a very challenging problem that requires analyses and measurements over extremely broad frequency bandwidth from DC to 50 GHz and above. This paper shares our experience in building a practical methodology to make predictable 50 Gbps interconnects models. Substantial part of interconnects can be simulated with transmission line models that require identification of causal broadband dielectric and conductor roughness models. It is shown that separation of losses between the conductor roughness and dielectric models is essential element of such identification. Examples of proper and improper material models identification and consequences are provided in the paper. Accurate prediction of interconnect behavior also requires localization and 3D EM analysis for all transitions or discontinuities. Examples of optimized interconnects designed for 50 Gbps channels and the validation with measurements are also provided. Author(s) Biography Wendemagegnehu (Wendem) T. Beyene received his B.S. and M.S. degrees in Electrical Engineering from Columbia University, in 1988 and 1991 respectively, and his Ph.D. degree in Electrical and Computer Engineering from University of Illinois at Urbana-Champaign, in 1997. In the past, he was employed by IBM, Hewlett-Packard, and Agilent Technologies. He is currently a technical director at Rambus Inc. where he is responsible for signal and power integrity of multi-gigabit serial and parallel interfaces. Yeon-Chang Hahm received his M.S. and Ph.D. degrees in Electrical and Computer Engineering from Oregon State University in 1997 and 2000 respectively. His academic research area focuses on computing distributed elements of on-chip interconnects and modeling. After receiving his degree, he joined IBM, AMD consecutively and worked on SI/PI area for 12 years. He is currently a Principal Engineer at Rambus Inc. responsible for electrical modeling of on-board & on-package passives as well as SI simulations of high-speed serial and parallel signals. Jihong Ren received her PhD degree in Computer Science from University of British Columbia, Vancouver, Canada in 2006, where she worked on optimal equalization for chip-to-chip high-speed buses. She is currently a Senior Manager at Altera, managing the SerDes IO architecture group. Prior to Altera, she was with Rambus Inc., managing the Signal Integrity and Power Integrity team. She authored and co-authored more than thirty papers, four book chapters and filed 14 patent applications in high-speed communications area. She was awarded the silver Distinguished Inventor award from Rambus in 2010. Dave Secker is currently a Technical Director in Systems Engineering at Rambus Inc., where he has been for the past 17 years. His responsibilities include physical design, modeling and optimization of high-speed signal interconnect and power delivery 3 networks at the IC package and system board levels. Previously he worked at Los Alamos National Laboratory as a research assistant. Mr. Secker received his M.S. degree in Electrical and Computer Engineering from The University of Arizona in 1996. Don Mullen is currently a Senior Principal Engineer at Rambus Inc., focusing on systems packaging, mechanical, and thermal design; he has been at Rambus for the past 15 years. Prior to Rambus, he held various engineering positions involving electronic packaging, thermal design, biomedical engineering, and mechanical systems engineering design. He has a BSME ('70) and is a registered professional engineer in California..

2015 IEEE 65th Electronic Components and Technology Conference (ECTC), 2015

The development of the next generation serial interfaces that operate between 50 Gbps and 60 Gbps... more The development of the next generation serial interfaces that operate between 50 Gbps and 60 Gbps is underway to deploy 400 Gb/s Ethernet systems. Design, analysis, and characterization of passive channels at these data rates are very challenging. Advanced modeling, analysis, and improved measurement techniques are required to accurately characterize high-speed links over broad frequency ranges. This paper describes the design and measurement used to characterize high-speed interconnects: boards, packages, and connectors including transition structures. Various interconnect components including several boards with various PCB laminates, backplanes with one and two connectors, straight through and orthogonal midplanes, chip-to-chip, and chip-to-module systems with transmitter and receiver packages are built and measured. Since both NRZ and PAM-4 signaling are presently under consideration for these new interfaces, the optimized interconnects are then analyzed using various equalization and these two signaling techniques at data rate of 56 Gbps. The resulting link performance is provided for the measured interconnect systems.

2014 IEEE 64th Electronic Components and Technology Conference (ECTC), 2014

The design of interconnects for links operating at 50 Gbps and beyond is very challenging. The lo... more The design of interconnects for links operating at 50 Gbps and beyond is very challenging. The loss, dispersion, and discontinuities along the signaling path have to be minimized over a wide frequency range. Frequency dependent material properties and surface roughness has to be accurately considered. The impacts of short via stubs that are ignored at lower data rates can severely degrade the signals when operating at higher data rates. In order to provide ways to mitigate these effects and optimize the performance of the system, it is primarily essential to correctly model and characterize the passive channel. In this paper, the modeling and characterization techniques that guarantee successful designs of passive channels for data rates of 50 Gbps and beyond will be presented. Detailed studies and measurement results on the effects of short via stubs are also presented.

IEEE Transactions on Microwave Theory and Techniques, 2000

A new, comprehensive CAD-oriented modeling methodology for single and coupled interconnects on an... more A new, comprehensive CAD-oriented modeling methodology for single and coupled interconnects on an Si-SiO 2 substrate is presented. The modeling technique uses a modified quasi-static spectral domain electromagnetic analysis which takes into account the skin effect in the semiconducting substrate. equivalent-circuit models with only ideal lumped elements, representing the broadband characteristics of the interconnects, are extracted. The response of the proposed SPICE compatible equivalent-circuit models is shown to be in good agreement with the frequency-dependent transmission line characteristics of single and general coupled on-chip interconnects.

Electronics Letters, 1998

The layout of the switching element is shown in Fig. lb. The central narrow line, 1 0 p wide and ... more The layout of the switching element is shown in Fig. lb. The central narrow line, 1 0 p wide and 1.5" long, is the S-N switching element. The radial chokes are used as the capacitors in shunt and the 70pm wide lines are used as the inductances L, in series. The substrate area is 5 x 10 mm3.

With increasing operating frequencies in CMOS RF/microwave integrated circuits, the performance o... more With increasing operating frequencies in CMOS RF/microwave integrated circuits, the performance of on-chip interconnects is becoming significantly affected by the lossy substrate. It is the purpose of the first part of this thesis to develop a rigorous field theoretic analysis approach for ...

2017 IEEE 67th Electronic Components and Technology Conference (ECTC)

2015 IEEE 65th Electronic Components and Technology Conference (ECTC), 2015

The development of the next generation serial interfaces that operate between 50 Gbps and 60 Gbps... more The development of the next generation serial interfaces that operate between 50 Gbps and 60 Gbps is underway to deploy 400 Gb/s Ethernet systems. Design, analysis, and characterization of passive channels at these data rates are very challenging. Advanced modeling, analysis, and improved measurement techniques are required to accurately characterize high-speed links over broad frequency ranges. This paper describes the design and measurement used to characterize high-speed interconnects: boards, packages, and connectors including transition structures. Various interconnect components including several boards with various PCB laminates, backplanes with one and two connectors, straight through and orthogonal midplanes, chip-to-chip, and chip-to-module systems with transmitter and receiver packages are built and measured. Since both NRZ and PAM-4 signaling are presently under consideration for these new interfaces, the optimized interconnects are then analyzed using various equalization and these two signaling techniques at data rate of 56 Gbps. The resulting link performance is provided for the measured interconnect systems.

2014 IEEE 64th Electronic Components and Technology Conference (ECTC), 2014

Design of PCB interconnects for data channels running at bitrate 50 Gbps and beyond is a very cha... more Design of PCB interconnects for data channels running at bitrate 50 Gbps and beyond is a very challenging problem that requires analyses and measurements over extremely broad frequency bandwidth from DC to 50 GHz and above. This paper shares our experience in building a practical methodology to make predictable 50 Gbps interconnects models. Substantial part of interconnects can be simulated with transmission line models that require identification of causal broadband dielectric and conductor roughness models. It is shown that separation of losses between the conductor roughness and dielectric models is essential element of such identification. Examples of proper and improper material models identification and consequences are provided in the paper. Accurate prediction of interconnect behavior also requires localization and 3D EM analysis for all transitions or discontinuities. Examples of optimized interconnects designed for 50 Gbps channels and the validation with measurements are also provided. Author(s) Biography Wendemagegnehu (Wendem) T. Beyene received his B.S. and M.S. degrees in Electrical Engineering from Columbia University, in 1988 and 1991 respectively, and his Ph.D. degree in Electrical and Computer Engineering from University of Illinois at Urbana-Champaign, in 1997. In the past, he was employed by IBM, Hewlett-Packard, and Agilent Technologies. He is currently a technical director at Rambus Inc. where he is responsible for signal and power integrity of multi-gigabit serial and parallel interfaces. Yeon-Chang Hahm received his M.S. and Ph.D. degrees in Electrical and Computer Engineering from Oregon State University in 1997 and 2000 respectively. His academic research area focuses on computing distributed elements of on-chip interconnects and modeling. After receiving his degree, he joined IBM, AMD consecutively and worked on SI/PI area for 12 years. He is currently a Principal Engineer at Rambus Inc. responsible for electrical modeling of on-board & on-package passives as well as SI simulations of high-speed serial and parallel signals. Jihong Ren received her PhD degree in Computer Science from University of British Columbia, Vancouver, Canada in 2006, where she worked on optimal equalization for chip-to-chip high-speed buses. She is currently a Senior Manager at Altera, managing the SerDes IO architecture group. Prior to Altera, she was with Rambus Inc., managing the Signal Integrity and Power Integrity team. She authored and co-authored more than thirty papers, four book chapters and filed 14 patent applications in high-speed communications area. She was awarded the silver Distinguished Inventor award from Rambus in 2010. Dave Secker is currently a Technical Director in Systems Engineering at Rambus Inc., where he has been for the past 17 years. His responsibilities include physical design, modeling and optimization of high-speed signal interconnect and power delivery 3 networks at the IC package and system board levels. Previously he worked at Los Alamos National Laboratory as a research assistant. Mr. Secker received his M.S. degree in Electrical and Computer Engineering from The University of Arizona in 1996. Don Mullen is currently a Senior Principal Engineer at Rambus Inc., focusing on systems packaging, mechanical, and thermal design; he has been at Rambus for the past 15 years. Prior to Rambus, he held various engineering positions involving electronic packaging, thermal design, biomedical engineering, and mechanical systems engineering design. He has a BSME ('70) and is a registered professional engineer in California..

2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 2016

Advanced memory technologies such as DDR4 and LPDDR4 are able to receive and transmit huge amount... more Advanced memory technologies such as DDR4 and LPDDR4 are able to receive and transmit huge amount of data in faster and more efficient ways than ever before. At the same time, reducing power noise and designing dense traces become a challenging part of the design processes. In particular, high signal density on a package naturally restricts the resources for robust power delivery when keeping the same package layer count. While the costly thin-core packaging technology is widely available, embedded trace substrate (ETS) packaging technology is another viable solution at a reduced price. This work employs ETS substrate with careful signal designs and deployments of power planes. Essential part of the ETS package design includes the power delivery network (PDN) design in conjunction with Power Supply Induced Jitter (PSIJ) sensitivity from the silicon circuits. At the same time, critical components of the power rail noise needs to be suppressed by on-die and on-package decoupling capacitances. After iterative designs and simulations for ETS package, about 92% of overall PDN noise and 86%~95% of jitter impact were estimated compared to thin-core package, and 88% of tJIT(per) and 93% of tJIT(cc) have been achieved in the measurements.

Electronics Letters, 1998

Experimental results: The results of measurement of the SN switch at T = 65K are shown in Figs. 2... more Experimental results: The results of measurement of the SN switch at T = 65K are shown in Figs. 2 and 3. In the S-state (Fig. 2) the insertion loss level does not exceed 4.ldB. The N-state (Fig. 3) was observed under a DC control current of 40mA. The isolation in the whole ...

The development of pover electronic devices and various microprocessor control techniques have be... more The development of pover electronic devices and various microprocessor control techniques have been surmounting the critical point of the nonlinear characteristics in electric machine drives, and the results made more use of the AC motor system. But, veil known technique to drive AC machine in recent days, SPWM inverter-fed induction machine produces mechanically and electrically generated unpleasant audible noise.

Design of PCB interconnects for data channels running at bitrate 50 Gbps and beyond is a very cha... more Design of PCB interconnects for data channels running at bitrate 50 Gbps and beyond is a very challenging problem that requires analyses and measurements over extremely broad frequency bandwidth from DC to 50 GHz and above. This paper shares our experience in building a practical methodology to make predictable 50 Gbps interconnects models. Substantial part of interconnects can be simulated with transmission line models that require identification of causal broadband dielectric and conductor roughness models. It is shown that separation of losses between the conductor roughness and dielectric models is essential element of such identification. Examples of proper and improper material models identification and consequences are provided in the paper. Accurate prediction of interconnect behavior also requires localization and 3D EM analysis for all transitions or discontinuities. Examples of optimized interconnects designed for 50 Gbps channels and the validation with measurements are also provided. Author(s) Biography Wendemagegnehu (Wendem) T. Beyene received his B.S. and M.S. degrees in Electrical Engineering from Columbia University, in 1988 and 1991 respectively, and his Ph.D. degree in Electrical and Computer Engineering from University of Illinois at Urbana-Champaign, in 1997. In the past, he was employed by IBM, Hewlett-Packard, and Agilent Technologies. He is currently a technical director at Rambus Inc. where he is responsible for signal and power integrity of multi-gigabit serial and parallel interfaces. Yeon-Chang Hahm received his M.S. and Ph.D. degrees in Electrical and Computer Engineering from Oregon State University in 1997 and 2000 respectively. His academic research area focuses on computing distributed elements of on-chip interconnects and modeling. After receiving his degree, he joined IBM, AMD consecutively and worked on SI/PI area for 12 years. He is currently a Principal Engineer at Rambus Inc. responsible for electrical modeling of on-board & on-package passives as well as SI simulations of high-speed serial and parallel signals. Jihong Ren received her PhD degree in Computer Science from University of British Columbia, Vancouver, Canada in 2006, where she worked on optimal equalization for chip-to-chip high-speed buses. She is currently a Senior Manager at Altera, managing the SerDes IO architecture group. Prior to Altera, she was with Rambus Inc., managing the Signal Integrity and Power Integrity team. She authored and co-authored more than thirty papers, four book chapters and filed 14 patent applications in high-speed communications area. She was awarded the silver Distinguished Inventor award from Rambus in 2010. Dave Secker is currently a Technical Director in Systems Engineering at Rambus Inc., where he has been for the past 17 years. His responsibilities include physical design, modeling and optimization of high-speed signal interconnect and power delivery 3 networks at the IC package and system board levels. Previously he worked at Los Alamos National Laboratory as a research assistant. Mr. Secker received his M.S. degree in Electrical and Computer Engineering from The University of Arizona in 1996. Don Mullen is currently a Senior Principal Engineer at Rambus Inc., focusing on systems packaging, mechanical, and thermal design; he has been at Rambus for the past 15 years. Prior to Rambus, he held various engineering positions involving electronic packaging, thermal design, biomedical engineering, and mechanical systems engineering design. He has a BSME ('70) and is a registered professional engineer in California..

2015 IEEE 65th Electronic Components and Technology Conference (ECTC), 2015

The development of the next generation serial interfaces that operate between 50 Gbps and 60 Gbps... more The development of the next generation serial interfaces that operate between 50 Gbps and 60 Gbps is underway to deploy 400 Gb/s Ethernet systems. Design, analysis, and characterization of passive channels at these data rates are very challenging. Advanced modeling, analysis, and improved measurement techniques are required to accurately characterize high-speed links over broad frequency ranges. This paper describes the design and measurement used to characterize high-speed interconnects: boards, packages, and connectors including transition structures. Various interconnect components including several boards with various PCB laminates, backplanes with one and two connectors, straight through and orthogonal midplanes, chip-to-chip, and chip-to-module systems with transmitter and receiver packages are built and measured. Since both NRZ and PAM-4 signaling are presently under consideration for these new interfaces, the optimized interconnects are then analyzed using various equalization and these two signaling techniques at data rate of 56 Gbps. The resulting link performance is provided for the measured interconnect systems.

2014 IEEE 64th Electronic Components and Technology Conference (ECTC), 2014

The design of interconnects for links operating at 50 Gbps and beyond is very challenging. The lo... more The design of interconnects for links operating at 50 Gbps and beyond is very challenging. The loss, dispersion, and discontinuities along the signaling path have to be minimized over a wide frequency range. Frequency dependent material properties and surface roughness has to be accurately considered. The impacts of short via stubs that are ignored at lower data rates can severely degrade the signals when operating at higher data rates. In order to provide ways to mitigate these effects and optimize the performance of the system, it is primarily essential to correctly model and characterize the passive channel. In this paper, the modeling and characterization techniques that guarantee successful designs of passive channels for data rates of 50 Gbps and beyond will be presented. Detailed studies and measurement results on the effects of short via stubs are also presented.

IEEE Transactions on Microwave Theory and Techniques, 2000

A new, comprehensive CAD-oriented modeling methodology for single and coupled interconnects on an... more A new, comprehensive CAD-oriented modeling methodology for single and coupled interconnects on an Si-SiO 2 substrate is presented. The modeling technique uses a modified quasi-static spectral domain electromagnetic analysis which takes into account the skin effect in the semiconducting substrate. equivalent-circuit models with only ideal lumped elements, representing the broadband characteristics of the interconnects, are extracted. The response of the proposed SPICE compatible equivalent-circuit models is shown to be in good agreement with the frequency-dependent transmission line characteristics of single and general coupled on-chip interconnects.

Electronics Letters, 1998

The layout of the switching element is shown in Fig. lb. The central narrow line, 1 0 p wide and ... more The layout of the switching element is shown in Fig. lb. The central narrow line, 1 0 p wide and 1.5" long, is the S-N switching element. The radial chokes are used as the capacitors in shunt and the 70pm wide lines are used as the inductances L, in series. The substrate area is 5 x 10 mm3.

With increasing operating frequencies in CMOS RF/microwave integrated circuits, the performance o... more With increasing operating frequencies in CMOS RF/microwave integrated circuits, the performance of on-chip interconnects is becoming significantly affected by the lossy substrate. It is the purpose of the first part of this thesis to develop a rigorous field theoretic analysis approach for ...

2017 IEEE 67th Electronic Components and Technology Conference (ECTC)

2015 IEEE 65th Electronic Components and Technology Conference (ECTC), 2015

The development of the next generation serial interfaces that operate between 50 Gbps and 60 Gbps... more The development of the next generation serial interfaces that operate between 50 Gbps and 60 Gbps is underway to deploy 400 Gb/s Ethernet systems. Design, analysis, and characterization of passive channels at these data rates are very challenging. Advanced modeling, analysis, and improved measurement techniques are required to accurately characterize high-speed links over broad frequency ranges. This paper describes the design and measurement used to characterize high-speed interconnects: boards, packages, and connectors including transition structures. Various interconnect components including several boards with various PCB laminates, backplanes with one and two connectors, straight through and orthogonal midplanes, chip-to-chip, and chip-to-module systems with transmitter and receiver packages are built and measured. Since both NRZ and PAM-4 signaling are presently under consideration for these new interfaces, the optimized interconnects are then analyzed using various equalization and these two signaling techniques at data rate of 56 Gbps. The resulting link performance is provided for the measured interconnect systems.

2014 IEEE 64th Electronic Components and Technology Conference (ECTC), 2014

Design of PCB interconnects for data channels running at bitrate 50 Gbps and beyond is a very cha... more Design of PCB interconnects for data channels running at bitrate 50 Gbps and beyond is a very challenging problem that requires analyses and measurements over extremely broad frequency bandwidth from DC to 50 GHz and above. This paper shares our experience in building a practical methodology to make predictable 50 Gbps interconnects models. Substantial part of interconnects can be simulated with transmission line models that require identification of causal broadband dielectric and conductor roughness models. It is shown that separation of losses between the conductor roughness and dielectric models is essential element of such identification. Examples of proper and improper material models identification and consequences are provided in the paper. Accurate prediction of interconnect behavior also requires localization and 3D EM analysis for all transitions or discontinuities. Examples of optimized interconnects designed for 50 Gbps channels and the validation with measurements are also provided. Author(s) Biography Wendemagegnehu (Wendem) T. Beyene received his B.S. and M.S. degrees in Electrical Engineering from Columbia University, in 1988 and 1991 respectively, and his Ph.D. degree in Electrical and Computer Engineering from University of Illinois at Urbana-Champaign, in 1997. In the past, he was employed by IBM, Hewlett-Packard, and Agilent Technologies. He is currently a technical director at Rambus Inc. where he is responsible for signal and power integrity of multi-gigabit serial and parallel interfaces. Yeon-Chang Hahm received his M.S. and Ph.D. degrees in Electrical and Computer Engineering from Oregon State University in 1997 and 2000 respectively. His academic research area focuses on computing distributed elements of on-chip interconnects and modeling. After receiving his degree, he joined IBM, AMD consecutively and worked on SI/PI area for 12 years. He is currently a Principal Engineer at Rambus Inc. responsible for electrical modeling of on-board & on-package passives as well as SI simulations of high-speed serial and parallel signals. Jihong Ren received her PhD degree in Computer Science from University of British Columbia, Vancouver, Canada in 2006, where she worked on optimal equalization for chip-to-chip high-speed buses. She is currently a Senior Manager at Altera, managing the SerDes IO architecture group. Prior to Altera, she was with Rambus Inc., managing the Signal Integrity and Power Integrity team. She authored and co-authored more than thirty papers, four book chapters and filed 14 patent applications in high-speed communications area. She was awarded the silver Distinguished Inventor award from Rambus in 2010. Dave Secker is currently a Technical Director in Systems Engineering at Rambus Inc., where he has been for the past 17 years. His responsibilities include physical design, modeling and optimization of high-speed signal interconnect and power delivery 3 networks at the IC package and system board levels. Previously he worked at Los Alamos National Laboratory as a research assistant. Mr. Secker received his M.S. degree in Electrical and Computer Engineering from The University of Arizona in 1996. Don Mullen is currently a Senior Principal Engineer at Rambus Inc., focusing on systems packaging, mechanical, and thermal design; he has been at Rambus for the past 15 years. Prior to Rambus, he held various engineering positions involving electronic packaging, thermal design, biomedical engineering, and mechanical systems engineering design. He has a BSME ('70) and is a registered professional engineer in California..

2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 2016

Advanced memory technologies such as DDR4 and LPDDR4 are able to receive and transmit huge amount... more Advanced memory technologies such as DDR4 and LPDDR4 are able to receive and transmit huge amount of data in faster and more efficient ways than ever before. At the same time, reducing power noise and designing dense traces become a challenging part of the design processes. In particular, high signal density on a package naturally restricts the resources for robust power delivery when keeping the same package layer count. While the costly thin-core packaging technology is widely available, embedded trace substrate (ETS) packaging technology is another viable solution at a reduced price. This work employs ETS substrate with careful signal designs and deployments of power planes. Essential part of the ETS package design includes the power delivery network (PDN) design in conjunction with Power Supply Induced Jitter (PSIJ) sensitivity from the silicon circuits. At the same time, critical components of the power rail noise needs to be suppressed by on-die and on-package decoupling capacitances. After iterative designs and simulations for ETS package, about 92% of overall PDN noise and 86%~95% of jitter impact were estimated compared to thin-core package, and 88% of tJIT(per) and 93% of tJIT(cc) have been achieved in the measurements.

Electronics Letters, 1998

Experimental results: The results of measurement of the SN switch at T = 65K are shown in Figs. 2... more Experimental results: The results of measurement of the SN switch at T = 65K are shown in Figs. 2 and 3. In the S-state (Fig. 2) the insertion loss level does not exceed 4.ldB. The N-state (Fig. 3) was observed under a DC control current of 40mA. The isolation in the whole ...