antoine reverdy - Academia.edu (original) (raw)
Papers by antoine reverdy
Laser Voltage Imaging: New Perspective Using Second Harmonic Detection on Submicron Technology
Proceedings, Nov 1, 2012
<jats:title>Abstract</jats:title> <jats:p>The Laser Voltage Imaging (LVI) techn... more <jats:title>Abstract</jats:title> <jats:p>The Laser Voltage Imaging (LVI) technique [1], introduced in 2009, appears as a very promising approach for Failure Analysis application which allows mapping frequencies through the backside of integrated circuits. In this paper, we propose a new range of application based on the study of the LVI second harmonic for signal degradation analysis. After a theoretical study of the impact of signal degradation on the second harmonic, we will demonstrate the interest of this new approach on two case studies on ultimate technology (28nm). This technique is a new approach of failure analysis that maps timing degradation and duty cycle degradation. In order to confirm the degradations we will use the LVP Technique. The last part is two real case studies on which this LVI second harmonic technique was used to find the root cause of a 28nm process issue.</jats:p>
Scan Chain Debug Using Dynamic Lock-In Thermography
Proceedings, Nov 1, 2011
In this paper, we demonstrate that lock-in thermography (LIT) appears as a key and complementary ... more In this paper, we demonstrate that lock-in thermography (LIT) appears as a key and complementary technique for Failure Analysis across different use cases. Even if the failure requires a complex emulation setup, thanks to a specific capability of our thermal system, this kind of failure can be addressed. In our FA case study, we will show that LIT is a most efficient solution to address a bridge defect located inside a complex logic area, and furthermore that LIT highlights the defect itself and not only the consequences of the defect.
Infrared Lock-In Thermography: From Localization of Low Power and Masked Defects to Absolute Temperature Mapping for Product Debug
Proceedings, Dec 1, 2019
<jats:title>Abstract</jats:title> <jats:p>The application of IR-Lock-In Thermog... more <jats:title>Abstract</jats:title> <jats:p>The application of IR-Lock-In Thermography (IRLIT) has been extended from 2D and 3D package fault isolation to on-die level analysis. In addition, the technique has become more sensitive allowing for detection of much lower dissipated power. In this paper, several fault localization cases covering PCB assemblies down to die level analysis are discussed using IR-LIT and absolute temperature mapping. Where possible, the analysis is complemented with physical defect verification. The fault isolation cases include an ultra-low power dissipation (&lt;150 nW) and several case studies with high ohmic connections. For the latter a new method based on phase mapping is discussed allowing for 2D localization of thermally invisible defects. The method will be demonstrated on a test vehicle where phase data extracted from a visible feature of the device under test is studied. After this, a case study at die level is presented in an attempt to distinguish the phase information from two stacked M2-M3 metallization layers of the Back-End Of the Line (BEOL). Finally, temperature mapping results of a 5 micron wide aluminum feature in silicon-oxide is presented that is pushing the optical resolution of the tool.</jats:p>
Localization of electrical active defects caused by reliability-related failure mechanism by the application of Lock-in Thermography
2013 IEEE International Reliability Physics Symposium (IRPS), 2013
Within this paper, the method of Lock-in Thermography (LIT) is presented and introduced as an use... more Within this paper, the method of Lock-in Thermography (LIT) is presented and introduced as an useful method for localizing electrical active defects caused by reliability-related failure mechanism. After a short introduction of the physical principle, several case studies are presented.
Infrared Lock-In Thermography: From Localization of Low Power and Masked Defects to Absolute Temperature Mapping for Product Debug
<jats:title>Abstract</jats:title> <jats:p>The application of IR-Lock-In Thermog... more <jats:title>Abstract</jats:title> <jats:p>The application of IR-Lock-In Thermography (IRLIT) has been extended from 2D and 3D package fault isolation to on-die level analysis. In addition, the technique has become more sensitive allowing for detection of much lower dissipated power. In this paper, several fault localization cases covering PCB assemblies down to die level analysis are discussed using IR-LIT and absolute temperature mapping. Where possible, the analysis is complemented with physical defect verification. The fault isolation cases include an ultra-low power dissipation (&lt;150 nW) and several case studies with high ohmic connections. For the latter a new method based on phase mapping is discussed allowing for 2D localization of thermally invisible defects. The method will be demonstrated on a test vehicle where phase data extracted from a visible feature of the device under test is studied. After this, a case study at die level is presented in an attempt to distinguish the phase information from two stacked M2-M3 metallization layers of the Back-End Of the Line (BEOL). Finally, temperature mapping results of a 5 micron wide aluminum feature in silicon-oxide is presented that is pushing the optical resolution of the tool.</jats:p>
Scan chain debug using Dynamic Lock-In Thermography
In this paper, we demonstrate that lock-in thermography (LIT) appears as a key and complementary ... more In this paper, we demonstrate that lock-in thermography (LIT) appears as a key and complementary technique for Failure Analysis across different use cases. Even if the failure requires a complex emulation setup, thanks to a specific capability of our thermal system, this kind of failure can be addressed. In our FA case study, we will show that LIT is a most efficient solution to address a bridge defect located inside a complex logic area, and furthermore that LIT highlights the defect itself and not only the consequences of the defect.
Thermischen Laserstimulation durch eine Seite des Geräts beim Erfassen von thermischen Strahlungsbildern auf der gegenüberliegenden Seite mittels das Lock-In verfahren
Precise Localization of 28 nm via Chain Resistive Defect Using EBAC and Nanoprobing
International Symposium for Testing and Failure Analysis, 2012
As technology nodes continue to shrink, resistive opens have become increasingly difficult to det... more As technology nodes continue to shrink, resistive opens have become increasingly difficult to detect using conventional methods such as AVC and PVC. The failure isolation method, Electron Beam Absorbed Current (EBAC) Imaging has recently become the preferred method in failure analysis labs for fast and highly accurate detection of resistive opens and shorts on a number of structures. This paper presents a case study using a two nanoprobe EBAC technique on a 28nm node test structure. This technique pinpointed the fail and allowed direct TEM lamella.
Laser Voltage Imaging: New Perspective Using Second Harmonic Detection on Submicron Technology
<jats:title>Abstract</jats:title> <jats:p>The Laser Voltage Imaging (LVI) techn... more <jats:title>Abstract</jats:title> <jats:p>The Laser Voltage Imaging (LVI) technique [1], introduced in 2009, appears as a very promising approach for Failure Analysis application which allows mapping frequencies through the backside of integrated circuits. In this paper, we propose a new range of application based on the study of the LVI second harmonic for signal degradation analysis. After a theoretical study of the impact of signal degradation on the second harmonic, we will demonstrate the interest of this new approach on two case studies on ultimate technology (28nm). This technique is a new approach of failure analysis that maps timing degradation and duty cycle degradation. In order to confirm the degradations we will use the LVP Technique. The last part is two real case studies on which this LVI second harmonic technique was used to find the root cause of a 28nm process issue.</jats:p>
3-D Defect Localization by Measurement and Modeling of the Dynamics of Heat Transport in Deep Sub-Micron Devices
ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis, 2007
Due to relentless down scaling of device geometries, failure analysis is getting more and more co... more Due to relentless down scaling of device geometries, failure analysis is getting more and more complex. As a matter of fact, the success rate of Thermal Laser Stimulation (TLS) techniques drops significantly for 90/65 nm CMOS devices because of the lack of x, y and z accuracy. In our aim to improve the TLS based fault isolation method, we have studied thermal time-constant signatures using a Modulated Optical Beam Induced Resistance Change (MOBIRCH) technique that may provide accurate x and y submicron resolution as well as depth or z-information of defects in the interconnection part of devices. Both Modeling and measurement results indicate that OBIRCH signal phase shifts and heat-up & cool-down time constants indeed do correlate with the location, dimensions and density of the structures studied.
Differentiation between artifacts and true defects in 45 nm BEOL structures in M-TLS technique
ABSTRACT
Localisation de défauts par stimulation thermique laser modulée en intensité : développement et application à la direction de phase
Au cours de ce manuscrit de these nous abordons les differentes techniques mises en œuvre dans la... more Au cours de ce manuscrit de these nous abordons les differentes techniques mises en œuvre dans la localisation de defauts dans la partie interconnexion des circuits microelectroniques avec une attention toute particuliere sur la Stimulation Thermique Laser (STL) et ses limitations. Une etude plus theorique sur la modelisation des reponses thermiques de structures elementaires soumises a un echelon de puissance thermique est ensuite developpee. Elle debouche sur un modele analytique qui va permettre l’identification de parametres caracteristiques des variations temporelles de la reponse en STL indicielle. Nous demontrons par la suite l’interet de cette nouvelle approche sur l’analyse de defaillance des Circuits Integres, sur une structure de test non defaillante, caracteristique de la partie d’interconnexion des circuits integres. Le troisieme chapitre est dedie a l’evolution de la demarche experimentale, dans le but d’acceder a l’information sur la dynamique de variation du signal d...
Enhanced package- and die-level defect localization by dynamic lock-in thermography
Recent improvements of microscopic Lock-In Thermography (LIT) offer the non-destructive localizat... more Recent improvements of microscopic Lock-In Thermography (LIT) offer the non-destructive localization of thermally active defects like shorts or resistive opens, even through the full package. This paper briefly discusses LIT based analysis flow highlighting benefits of the combination with 3D x-ray. The main focus of the paper is to discuss and demonstrate different ways how to activate the thermally active defects with more complex Devices Under Test (DUTs) / defect signatures, requiring Automated Test Equipment (ATE) docking.
Use of Analog Simulation in Failure Analysis: Application to Emission Microscopy and Laser Voltage Probing Techniques
This paper describes a novel flow using analog simulations for the failure analysis of digital, a... more This paper describes a novel flow using analog simulations for the failure analysis of digital, analog, and mixed signal devices. Although cell level diagnosis tools are available in the industry, it presents a solution through analog intra-cell simulation particularly advantageous when multiple defects give the same fault result at cell level. Details of case studies such as the one analog intracell simulation on digital device and the analog laser voltage probing are covered. The aim of the simulation solution proposed is to support the failure analyst to interpret emission images on analog devices. The presented analog simulation flow consists of computing the current (or current density) in MOS and bipolar transistors and simulating the internal waveforms in digital or analog cells. It enables failure analysts to interpret light emission and laser voltage probing results obtained on a physical device in a fast and efficient way.
Electro Optical Terahertz Pulse Reflectometry, a non destructive technique to localize defects on various type of package
Abstract Localizing defects (particularly, dead open and resistive open defects) at package level... more Abstract Localizing defects (particularly, dead open and resistive open defects) at package level is becoming a critical challenge for Failure Analysis Laboratories due to package miniaturisation and increased complexity. One of the well-known approaches to address this set of problems within a Device Under Test (DUT) is Time Domain Reflectometry (TDR). The main limitation of this technique is the lack of distance-to-defect accuracy and sensitivity. Electro Optical Terahertz Pulse Reflectometry (EOTPR) overcomes these limitations by using photoconductive terahertz generation and detection technology, resulting in a system with: (i) high measurement bandwidth, (ii) extremely low time base jitter, and (iii) high time base accuracy and range with greater sensitivity. In this paper we present case studies in which EOTPR has been successfully applied to a series of different device types.
Microelectronics Reliability, 2008
Thermal laser stimulation on sub-Micronics interconnection structures is well known. The usual ap... more Thermal laser stimulation on sub-Micronics interconnection structures is well known. The usual approach is to consider them as a resistor, whatever the structure is. We experimentally showed the weaknesses of this assumption which has to be reconsidered. In this paper we develop a new analytical model based on fine characterization of the dynamic behavior structure heated and cooled. In addition to a better understanding of thermal laser stimulation signature, this modelization opens a wide range of application: structure identification, 3-D localization, etc. It should be a key for failure analysis accuracy and efficiency on Back End Of the Line test structures.
Fast and rigorous use of thermal time constant to characterize back end of the line test structure in advanced technology
Microelectronics Reliability, 2008
ABSTRACT Thermal time constant analysis (TTC) opens a wide range of applications: structure ident... more ABSTRACT Thermal time constant analysis (TTC) opens a wide range of applications: structure identification, 3D localization for very deep micron technologies. In this paper, we describe a new analysis methodology for TTC signatures induced by modulated thermal laser stimulation (TLS). Previous approaches did not allow a fast and rigorous method to acquire and treat transient TLS signals. To overcome these limitations we have done a theoretical study, based on the Fourier transform of an analytical model describing temporal dependency of the TLS signal, which is powerful for signature interpretation. This analysis flow is applied to 65 nm reliability test structure.
Exploitation of Laser Voltage techniques for identification and complete characterization of a scan chain transition fail issue using the second harmonic approach
Microelectronics Reliability
Localisation de défauts par stimulation thermique laser modulée en intensité : développement et application à la direction de phase
Http Www Theses Fr, 2008
Introduction of Spectral Mapping through Transmission Grating, Derivative Technique of Photon Emission
ABSTRACT We are introducing an extension technique to photo emission in order to provide more ins... more ABSTRACT We are introducing an extension technique to photo emission in order to provide more insights to the emission spots in the field of view allowing to recognize the faulty transistor or a short, a diffraction grating is incorporated in the optical path of our system so that we can display the spectrum of each emission spots in the field of view.
Laser Voltage Imaging: New Perspective Using Second Harmonic Detection on Submicron Technology
Proceedings, Nov 1, 2012
<jats:title>Abstract</jats:title> <jats:p>The Laser Voltage Imaging (LVI) techn... more <jats:title>Abstract</jats:title> <jats:p>The Laser Voltage Imaging (LVI) technique [1], introduced in 2009, appears as a very promising approach for Failure Analysis application which allows mapping frequencies through the backside of integrated circuits. In this paper, we propose a new range of application based on the study of the LVI second harmonic for signal degradation analysis. After a theoretical study of the impact of signal degradation on the second harmonic, we will demonstrate the interest of this new approach on two case studies on ultimate technology (28nm). This technique is a new approach of failure analysis that maps timing degradation and duty cycle degradation. In order to confirm the degradations we will use the LVP Technique. The last part is two real case studies on which this LVI second harmonic technique was used to find the root cause of a 28nm process issue.</jats:p>
Scan Chain Debug Using Dynamic Lock-In Thermography
Proceedings, Nov 1, 2011
In this paper, we demonstrate that lock-in thermography (LIT) appears as a key and complementary ... more In this paper, we demonstrate that lock-in thermography (LIT) appears as a key and complementary technique for Failure Analysis across different use cases. Even if the failure requires a complex emulation setup, thanks to a specific capability of our thermal system, this kind of failure can be addressed. In our FA case study, we will show that LIT is a most efficient solution to address a bridge defect located inside a complex logic area, and furthermore that LIT highlights the defect itself and not only the consequences of the defect.
Infrared Lock-In Thermography: From Localization of Low Power and Masked Defects to Absolute Temperature Mapping for Product Debug
Proceedings, Dec 1, 2019
<jats:title>Abstract</jats:title> <jats:p>The application of IR-Lock-In Thermog... more <jats:title>Abstract</jats:title> <jats:p>The application of IR-Lock-In Thermography (IRLIT) has been extended from 2D and 3D package fault isolation to on-die level analysis. In addition, the technique has become more sensitive allowing for detection of much lower dissipated power. In this paper, several fault localization cases covering PCB assemblies down to die level analysis are discussed using IR-LIT and absolute temperature mapping. Where possible, the analysis is complemented with physical defect verification. The fault isolation cases include an ultra-low power dissipation (&lt;150 nW) and several case studies with high ohmic connections. For the latter a new method based on phase mapping is discussed allowing for 2D localization of thermally invisible defects. The method will be demonstrated on a test vehicle where phase data extracted from a visible feature of the device under test is studied. After this, a case study at die level is presented in an attempt to distinguish the phase information from two stacked M2-M3 metallization layers of the Back-End Of the Line (BEOL). Finally, temperature mapping results of a 5 micron wide aluminum feature in silicon-oxide is presented that is pushing the optical resolution of the tool.</jats:p>
Localization of electrical active defects caused by reliability-related failure mechanism by the application of Lock-in Thermography
2013 IEEE International Reliability Physics Symposium (IRPS), 2013
Within this paper, the method of Lock-in Thermography (LIT) is presented and introduced as an use... more Within this paper, the method of Lock-in Thermography (LIT) is presented and introduced as an useful method for localizing electrical active defects caused by reliability-related failure mechanism. After a short introduction of the physical principle, several case studies are presented.
Infrared Lock-In Thermography: From Localization of Low Power and Masked Defects to Absolute Temperature Mapping for Product Debug
<jats:title>Abstract</jats:title> <jats:p>The application of IR-Lock-In Thermog... more <jats:title>Abstract</jats:title> <jats:p>The application of IR-Lock-In Thermography (IRLIT) has been extended from 2D and 3D package fault isolation to on-die level analysis. In addition, the technique has become more sensitive allowing for detection of much lower dissipated power. In this paper, several fault localization cases covering PCB assemblies down to die level analysis are discussed using IR-LIT and absolute temperature mapping. Where possible, the analysis is complemented with physical defect verification. The fault isolation cases include an ultra-low power dissipation (&lt;150 nW) and several case studies with high ohmic connections. For the latter a new method based on phase mapping is discussed allowing for 2D localization of thermally invisible defects. The method will be demonstrated on a test vehicle where phase data extracted from a visible feature of the device under test is studied. After this, a case study at die level is presented in an attempt to distinguish the phase information from two stacked M2-M3 metallization layers of the Back-End Of the Line (BEOL). Finally, temperature mapping results of a 5 micron wide aluminum feature in silicon-oxide is presented that is pushing the optical resolution of the tool.</jats:p>
Scan chain debug using Dynamic Lock-In Thermography
In this paper, we demonstrate that lock-in thermography (LIT) appears as a key and complementary ... more In this paper, we demonstrate that lock-in thermography (LIT) appears as a key and complementary technique for Failure Analysis across different use cases. Even if the failure requires a complex emulation setup, thanks to a specific capability of our thermal system, this kind of failure can be addressed. In our FA case study, we will show that LIT is a most efficient solution to address a bridge defect located inside a complex logic area, and furthermore that LIT highlights the defect itself and not only the consequences of the defect.
Thermischen Laserstimulation durch eine Seite des Geräts beim Erfassen von thermischen Strahlungsbildern auf der gegenüberliegenden Seite mittels das Lock-In verfahren
Precise Localization of 28 nm via Chain Resistive Defect Using EBAC and Nanoprobing
International Symposium for Testing and Failure Analysis, 2012
As technology nodes continue to shrink, resistive opens have become increasingly difficult to det... more As technology nodes continue to shrink, resistive opens have become increasingly difficult to detect using conventional methods such as AVC and PVC. The failure isolation method, Electron Beam Absorbed Current (EBAC) Imaging has recently become the preferred method in failure analysis labs for fast and highly accurate detection of resistive opens and shorts on a number of structures. This paper presents a case study using a two nanoprobe EBAC technique on a 28nm node test structure. This technique pinpointed the fail and allowed direct TEM lamella.
Laser Voltage Imaging: New Perspective Using Second Harmonic Detection on Submicron Technology
<jats:title>Abstract</jats:title> <jats:p>The Laser Voltage Imaging (LVI) techn... more <jats:title>Abstract</jats:title> <jats:p>The Laser Voltage Imaging (LVI) technique [1], introduced in 2009, appears as a very promising approach for Failure Analysis application which allows mapping frequencies through the backside of integrated circuits. In this paper, we propose a new range of application based on the study of the LVI second harmonic for signal degradation analysis. After a theoretical study of the impact of signal degradation on the second harmonic, we will demonstrate the interest of this new approach on two case studies on ultimate technology (28nm). This technique is a new approach of failure analysis that maps timing degradation and duty cycle degradation. In order to confirm the degradations we will use the LVP Technique. The last part is two real case studies on which this LVI second harmonic technique was used to find the root cause of a 28nm process issue.</jats:p>
3-D Defect Localization by Measurement and Modeling of the Dynamics of Heat Transport in Deep Sub-Micron Devices
ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis, 2007
Due to relentless down scaling of device geometries, failure analysis is getting more and more co... more Due to relentless down scaling of device geometries, failure analysis is getting more and more complex. As a matter of fact, the success rate of Thermal Laser Stimulation (TLS) techniques drops significantly for 90/65 nm CMOS devices because of the lack of x, y and z accuracy. In our aim to improve the TLS based fault isolation method, we have studied thermal time-constant signatures using a Modulated Optical Beam Induced Resistance Change (MOBIRCH) technique that may provide accurate x and y submicron resolution as well as depth or z-information of defects in the interconnection part of devices. Both Modeling and measurement results indicate that OBIRCH signal phase shifts and heat-up & cool-down time constants indeed do correlate with the location, dimensions and density of the structures studied.
Differentiation between artifacts and true defects in 45 nm BEOL structures in M-TLS technique
ABSTRACT
Localisation de défauts par stimulation thermique laser modulée en intensité : développement et application à la direction de phase
Au cours de ce manuscrit de these nous abordons les differentes techniques mises en œuvre dans la... more Au cours de ce manuscrit de these nous abordons les differentes techniques mises en œuvre dans la localisation de defauts dans la partie interconnexion des circuits microelectroniques avec une attention toute particuliere sur la Stimulation Thermique Laser (STL) et ses limitations. Une etude plus theorique sur la modelisation des reponses thermiques de structures elementaires soumises a un echelon de puissance thermique est ensuite developpee. Elle debouche sur un modele analytique qui va permettre l’identification de parametres caracteristiques des variations temporelles de la reponse en STL indicielle. Nous demontrons par la suite l’interet de cette nouvelle approche sur l’analyse de defaillance des Circuits Integres, sur une structure de test non defaillante, caracteristique de la partie d’interconnexion des circuits integres. Le troisieme chapitre est dedie a l’evolution de la demarche experimentale, dans le but d’acceder a l’information sur la dynamique de variation du signal d...
Enhanced package- and die-level defect localization by dynamic lock-in thermography
Recent improvements of microscopic Lock-In Thermography (LIT) offer the non-destructive localizat... more Recent improvements of microscopic Lock-In Thermography (LIT) offer the non-destructive localization of thermally active defects like shorts or resistive opens, even through the full package. This paper briefly discusses LIT based analysis flow highlighting benefits of the combination with 3D x-ray. The main focus of the paper is to discuss and demonstrate different ways how to activate the thermally active defects with more complex Devices Under Test (DUTs) / defect signatures, requiring Automated Test Equipment (ATE) docking.
Use of Analog Simulation in Failure Analysis: Application to Emission Microscopy and Laser Voltage Probing Techniques
This paper describes a novel flow using analog simulations for the failure analysis of digital, a... more This paper describes a novel flow using analog simulations for the failure analysis of digital, analog, and mixed signal devices. Although cell level diagnosis tools are available in the industry, it presents a solution through analog intra-cell simulation particularly advantageous when multiple defects give the same fault result at cell level. Details of case studies such as the one analog intracell simulation on digital device and the analog laser voltage probing are covered. The aim of the simulation solution proposed is to support the failure analyst to interpret emission images on analog devices. The presented analog simulation flow consists of computing the current (or current density) in MOS and bipolar transistors and simulating the internal waveforms in digital or analog cells. It enables failure analysts to interpret light emission and laser voltage probing results obtained on a physical device in a fast and efficient way.
Electro Optical Terahertz Pulse Reflectometry, a non destructive technique to localize defects on various type of package
Abstract Localizing defects (particularly, dead open and resistive open defects) at package level... more Abstract Localizing defects (particularly, dead open and resistive open defects) at package level is becoming a critical challenge for Failure Analysis Laboratories due to package miniaturisation and increased complexity. One of the well-known approaches to address this set of problems within a Device Under Test (DUT) is Time Domain Reflectometry (TDR). The main limitation of this technique is the lack of distance-to-defect accuracy and sensitivity. Electro Optical Terahertz Pulse Reflectometry (EOTPR) overcomes these limitations by using photoconductive terahertz generation and detection technology, resulting in a system with: (i) high measurement bandwidth, (ii) extremely low time base jitter, and (iii) high time base accuracy and range with greater sensitivity. In this paper we present case studies in which EOTPR has been successfully applied to a series of different device types.
Microelectronics Reliability, 2008
Thermal laser stimulation on sub-Micronics interconnection structures is well known. The usual ap... more Thermal laser stimulation on sub-Micronics interconnection structures is well known. The usual approach is to consider them as a resistor, whatever the structure is. We experimentally showed the weaknesses of this assumption which has to be reconsidered. In this paper we develop a new analytical model based on fine characterization of the dynamic behavior structure heated and cooled. In addition to a better understanding of thermal laser stimulation signature, this modelization opens a wide range of application: structure identification, 3-D localization, etc. It should be a key for failure analysis accuracy and efficiency on Back End Of the Line test structures.
Fast and rigorous use of thermal time constant to characterize back end of the line test structure in advanced technology
Microelectronics Reliability, 2008
ABSTRACT Thermal time constant analysis (TTC) opens a wide range of applications: structure ident... more ABSTRACT Thermal time constant analysis (TTC) opens a wide range of applications: structure identification, 3D localization for very deep micron technologies. In this paper, we describe a new analysis methodology for TTC signatures induced by modulated thermal laser stimulation (TLS). Previous approaches did not allow a fast and rigorous method to acquire and treat transient TLS signals. To overcome these limitations we have done a theoretical study, based on the Fourier transform of an analytical model describing temporal dependency of the TLS signal, which is powerful for signature interpretation. This analysis flow is applied to 65 nm reliability test structure.
Exploitation of Laser Voltage techniques for identification and complete characterization of a scan chain transition fail issue using the second harmonic approach
Microelectronics Reliability
Localisation de défauts par stimulation thermique laser modulée en intensité : développement et application à la direction de phase
Http Www Theses Fr, 2008
Introduction of Spectral Mapping through Transmission Grating, Derivative Technique of Photon Emission
ABSTRACT We are introducing an extension technique to photo emission in order to provide more ins... more ABSTRACT We are introducing an extension technique to photo emission in order to provide more insights to the emission spots in the field of view allowing to recognize the faulty transistor or a short, a diffraction grating is incorporated in the optical path of our system so that we can display the spectrum of each emission spots in the field of view.