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Papers by benjamín reyes
Revista de las Fuerzas Armadas
2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS), 2018
An 8-bit, 3.2 GS/s, time interleaved (TI) successive approximation register (SAR) analog-to-digit... more An 8-bit, 3.2 GS/s, time interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) with a non-buffered hierarchical demultiplexing architecture is proposed and fabricated. Compared to a typical hierarchical TI-ADC, (i) all track-and-hold (T&H) related noise sources and (ii) wide-band amplifiers for buffering of the input signal are avoided. In this way, the proposed solution can improve the signal-to-noise-ratio and reduce power consumption. The concept is demonstrated in an 8-bit 3.2 GS/s TI-ADC design based on 32 asynchronous SAR ADCs and fabricated in a 0.13μm CMOS process. The prototype includes (i) a programmable delay cell array to adjust four front sampling phases, and (ii) a 25.6 Gb/s low voltage differential signaling (LVDS) interface. Measurements of the fabricated TI-ADC show 44.6 dB of peak signal-to-noise-and-distortion ratio and 105 mW of power consumption at 1.2 V.
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019
An energy-efficient sampling architecture for time interleaved (TI) successive approximation regi... more An energy-efficient sampling architecture for time interleaved (TI) successive approximation register (SAR) analogto-digital converters (ADCs) is proposed. The architecture avoids the use of sampling buffers in order to minimize the number of noise sources on the input signal path and to reduce the power consumption on the track-and-hold (T&H) circuit. In addition, the noise optimization enables a size shrinking on the SAR ADC and, consequently, an extra power saving on the TI-ADC. This last optimization becomes particularly interesting in new CMOS technology nodes with high metal-capacitor matching. The tradeoffs of the typical hierarchical TI-ADC architecture are formulated and analyzed in comparison with this proposal. As an implementation example, an 8-bit 3.2-GS/s TI-ADC SAR is designed and fabricated in a 0.13-µm CMOS process. The implemented design uses four front sampling switches (phases), each one followed by eight asynchronous SAR ADCs. The design avoids all static current consumption across full input signal path up to digital output, pushing full TI-ADC efficiency to values similar to those achieved by the single SAR ADC unit. Measurements of the fabricated TI-ADC show 44.6-dB peak signal-to-noise-and-distortion ratio (7.12 effective number of bits) and 105-mW power consumption at 1.2 V.
Revista de las Fuerzas Armadas
2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS), 2018
An 8-bit, 3.2 GS/s, time interleaved (TI) successive approximation register (SAR) analog-to-digit... more An 8-bit, 3.2 GS/s, time interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) with a non-buffered hierarchical demultiplexing architecture is proposed and fabricated. Compared to a typical hierarchical TI-ADC, (i) all track-and-hold (T&H) related noise sources and (ii) wide-band amplifiers for buffering of the input signal are avoided. In this way, the proposed solution can improve the signal-to-noise-ratio and reduce power consumption. The concept is demonstrated in an 8-bit 3.2 GS/s TI-ADC design based on 32 asynchronous SAR ADCs and fabricated in a 0.13μm CMOS process. The prototype includes (i) a programmable delay cell array to adjust four front sampling phases, and (ii) a 25.6 Gb/s low voltage differential signaling (LVDS) interface. Measurements of the fabricated TI-ADC show 44.6 dB of peak signal-to-noise-and-distortion ratio and 105 mW of power consumption at 1.2 V.
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019
An energy-efficient sampling architecture for time interleaved (TI) successive approximation regi... more An energy-efficient sampling architecture for time interleaved (TI) successive approximation register (SAR) analogto-digital converters (ADCs) is proposed. The architecture avoids the use of sampling buffers in order to minimize the number of noise sources on the input signal path and to reduce the power consumption on the track-and-hold (T&H) circuit. In addition, the noise optimization enables a size shrinking on the SAR ADC and, consequently, an extra power saving on the TI-ADC. This last optimization becomes particularly interesting in new CMOS technology nodes with high metal-capacitor matching. The tradeoffs of the typical hierarchical TI-ADC architecture are formulated and analyzed in comparison with this proposal. As an implementation example, an 8-bit 3.2-GS/s TI-ADC SAR is designed and fabricated in a 0.13-µm CMOS process. The implemented design uses four front sampling switches (phases), each one followed by eight asynchronous SAR ADCs. The design avoids all static current consumption across full input signal path up to digital output, pushing full TI-ADC efficiency to values similar to those achieved by the single SAR ADC unit. Measurements of the fabricated TI-ADC show 44.6-dB peak signal-to-noise-and-distortion ratio (7.12 effective number of bits) and 105-mW power consumption at 1.2 V.