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An investigation of the effect of substrate loss on simultaneous switching noise (SSN) in on-chip... more An investigation of the effect of substrate loss on simultaneous switching noise (SSN) in on-chip power distribution networks is presented. In order to characterize the multi-layered power buses accurately for on-chip switching noise simulation, modelling of Vdd/ground rails over finite-resistivity substrates should include dielectric loss. The complete circuit model of power rails are then represented using RLCG elements. The waveform and propagation pattern of the noise are captured using finite difference time domain (FDTD) technique. This paper shows the effect of silicon substrate with different resistivities on the propagation of on-chip switching noise.
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In this paper, cascade-related approach and global one-single model methodology are investigated ... more In this paper, cascade-related approach and global one-single model methodology are investigated and compared in reference to real-world System-in-Package (SiP) product, which is designed using Cadence-SiP, and analyzed using Optimal SiP-enabled tool suite. A complete multi-level path, which consists of three portions-integrated circuit (IC), package and printed-circuit-board (PCB) -is selected as a test vehicle to investigate the limit of cascade-based approach. The results from quasi-static and full-wave simulation are compared, and the advantage of full-wave as well as limitation of quasi-static model are discussed. An innovative concept, referenced as "residual S-parameter", is proposed to characterize the coupling at the interface of IC, package and PCB, which plays an important role in the cascading of individual modules. Impact of the proposed concept on power integrity (PI) and signal integrity (SI) analysis is emphasized. Comparisons between full-wave, quasi-static and measurement results for representative component elements (interconnect, coupled bond wires) are discussed.
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IEEE Transactions on Advanced Packaging, 2001
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IEEE Topical Meeting on Electrical Performance of Electronic Packaging, 2003
This paper describes the effect of substrate loss on simultaneous switching noise (SSN) in on-chi... more This paper describes the effect of substrate loss on simultaneous switching noise (SSN) in on-chip power distribution networks (PDN). Conformal mapping and first-order Debye approximation based Finite Difference Time Domain (FDTD) have been used for model extraction and time domain simulation with frequency dependent parameters, respectively. The importance of substrate loss on power supply noise has been quantified in this paper.
Bookmarks Related papers MentionsView impact
An investigation of the effect of substrate loss on simultaneous switching noise (SSN) in on-chip... more An investigation of the effect of substrate loss on simultaneous switching noise (SSN) in on-chip power distribution networks is presented. In order to characterize the multi-layered power buses accurately for on-chip switching noise simulation, modelling of Vdd/ground rails over finite-resistivity substrates should include dielectric loss. The complete circuit model of power rails are then represented using RLCG elements. The waveform and propagation pattern of the noise are captured using finite difference time domain (FDTD) technique. This paper shows the effect of silicon substrate with different resistivities on the propagation of on-chip switching noise.
Bookmarks Related papers MentionsView impact
In this paper, cascade-related approach and global one-single model methodology are investigated ... more In this paper, cascade-related approach and global one-single model methodology are investigated and compared in reference to real-world System-in-Package (SiP) product, which is designed using Cadence-SiP, and analyzed using Optimal SiP-enabled tool suite. A complete multi-level path, which consists of three portions-integrated circuit (IC), package and printed-circuit-board (PCB) -is selected as a test vehicle to investigate the limit of cascade-based approach. The results from quasi-static and full-wave simulation are compared, and the advantage of full-wave as well as limitation of quasi-static model are discussed. An innovative concept, referenced as "residual S-parameter", is proposed to characterize the coupling at the interface of IC, package and PCB, which plays an important role in the cascading of individual modules. Impact of the proposed concept on power integrity (PI) and signal integrity (SI) analysis is emphasized. Comparisons between full-wave, quasi-static and measurement results for representative component elements (interconnect, coupled bond wires) are discussed.
Bookmarks Related papers MentionsView impact
IEEE Transactions on Advanced Packaging, 2001
Bookmarks Related papers MentionsView impact
IEEE Topical Meeting on Electrical Performance of Electronic Packaging, 2003
This paper describes the effect of substrate loss on simultaneous switching noise (SSN) in on-chi... more This paper describes the effect of substrate loss on simultaneous switching noise (SSN) in on-chip power distribution networks (PDN). Conformal mapping and first-order Debye approximation based Finite Difference Time Domain (FDTD) have been used for model extraction and time domain simulation with frequency dependent parameters, respectively. The importance of substrate loss on power supply noise has been quantified in this paper.
Bookmarks Related papers MentionsView impact