keith jenkins - Academia.edu (original) (raw)

Papers by keith jenkins

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)

A novel vertical bipolar transistor on SOI is proposed and demonstrated. The SOI silicon layer th... more A novel vertical bipolar transistor on SOI is proposed and demonstrated. The SOI silicon layer thickness is comparable to that used in SOI CMOS, and no subcollector layer or deep trench isolation are required. Simulated device characteristics are shown. The transistor is demonstrated in a polysilicon-emitter SiGe-base npn implementation on SOI with a 140-nm silicon layer. The fabricated npn bipolar transistors exhibit a BVceo of 4.2V and a peak f T of over 60GHz.

Extended Abstracts of the 2003 International Conference on Solid State Devices and Materials, 2003

2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, 2010

In this work, we studied current transport in mono-, biand tri-layer graphene. We find that both ... more In this work, we studied current transport in mono-, biand tri-layer graphene. We find that both the temperature and carrier density dependencies in monolayer and bi-/tri-layers are diametrically opposite. These difference can be understood by the different density-of-states and the additional screening of the electrical field of the substrate surface polar phonons in bi-layer/tri-layer graphenes. We also find that silicon nitride can provide uniform coverage of graphene in field-effect transistors while preserving the channel mobility. Using this insulator, we studied field-induced band-gap or band-overlap in graphene with various numbers of layers.

2011 International Electron Devices Meeting, 2011

High-frequency performance of graphene field-effect transistors (GFETs) with boron-nitride gate d... more High-frequency performance of graphene field-effect transistors (GFETs) with boron-nitride gate dielectrics is investigated. Devices show saturating IV characteristics and f max values as high as 34 GHz at 600-nm channel length. Bias dependence of f T and f max and the effect of the ambipolar channel on transconductance and output resistance are also examined.

Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena, 2010

Up to two layers of epitaxial graphene have been grown on the Si-face of 2 in. SiC wafers exhibit... more Up to two layers of epitaxial graphene have been grown on the Si-face of 2 in. SiC wafers exhibiting room-temperature Hall mobilities up to 2750 cm2 V−1 s−1, measured from ungated, large, 160×200 μm2 Hall bars, and up to 4000 cm2 V−1 s−1, from top-gated, small, 1×1.5 μm2 Hall bars. The growth process involved a combination of a cleaning step of the SiC in a Si-containing gas, followed by an annealing step in argon for epitaxial graphene formation. The structure and morphology of this graphene has been characterized using atomic force microscopy, high resolution transmission electron microscopy, and Raman spectroscopy. Furthermore, top-gated radio frequency field-effect transistors (rf-FETs) with a peak cutoff frequency fT of 100 GHz for a gate length of 240 nm were fabricated using epitaxial graphene grown on the Si-face of SiC that exhibited Hall mobilities up to 1450 cm2 V−1 s−1 from ungated Hall bars and 1575 cm2 V−1 s−1 from top-gated ones. This is by far the highest cutoff freq...

IEEE Journal of Solid-State Circuits, 2008

This paper presents an on-chip characterization method for random variation in minimum sized devi... more This paper presents an on-chip characterization method for random variation in minimum sized devices in nanometer technologies, using a sense amplifier-based test circuit. Instead of analog current measurements required in conventional techniques, the presented circuit operates using digital voltage measurements. Simulations of the test structure using predictive 70 nm and hardware based 0.13 m CMOS technologies show good accuracy (error 5%-10%) in the prediction of random variation even in the presence of systematic variations. A test chip is fabricated in 0.13 m bulk CMOS technology and measured to demonstrate the operation of the test structure.

2010 International Electron Devices Meeting, 2010

International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003., 2003

The effects of gate structure design on RF performance of strained-Si/SiGe nMODFETs are studied u... more The effects of gate structure design on RF performance of strained-Si/SiGe nMODFETs are studied using device simulation and experiments. It is found that while gate resistance only affects f max , fringing gate capacitance can have a significant impact on both f T and f max , indicating that the physical gate structure has to be optimized for any specific application. The experiments suggest that low-κ material is needed as sidewall spacer (if any) and passivation for reducing fringing gate capacitance. Furthermore, the simulations show that if low gate resistance can be achieved by using a multi-finger geometry, a rectangular-shaped gate should be used in order to reduce fringing gate capacitance. If not, a T-gate should be used to reduce gate resistance for high f max .

Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)

A "System on a Chip" is described, which integrates 16Mbits of DRAM, digital logic, SRAM, three P... more A "System on a Chip" is described, which integrates 16Mbits of DRAM, digital logic, SRAM, three PLLs, and a triple video Digital-to-analog converter in a 0.5 micron CMOS DRAM process. Application Specific Integrated Circuit (ASIC) techniques are employed, using multiple DRAM macros with Built-in Self Test (BIST), full Level-Sensitive Scan Design (LSSD) logic, and externally accessible analog circuitry. Issues regarding functional debugging, DRAM macro isolation and low cost manufacturing test using only a logic tester are described.

23rd IEEE VLSI Test Symposium (VTS'05)

This paper presents the design of an on-chip spectrum analyzer. A novel architecture is used to m... more This paper presents the design of an on-chip spectrum analyzer. A novel architecture is used to mitigate the problems encountered in trying to implement architectures employed in conventional stand-alone instruments on a chip. Specifically, it makes use of a very-low IF architecture, which leads to a highly compact design, that can be used for measuring the frequency content of high frequency on-chip signals. The architecture and design considerations along with an implementation in a 0.18 µm CMOS process is described. The design takes up an area of approximately 0.384 mm 2 with a simulated frequency range of 33 MHz to 3 GHz and a dynamic range of 60 dB.

Symposium on VLSI Technology, 1993

Very hi h performance 0.1 pm nMOSFETs are fabricated witf 3.5 nm gate oxide and shallow arsenic/b... more Very hi h performance 0.1 pm nMOSFETs are fabricated witf 3.5 nm gate oxide and shallow arsenic/boron (halo) source-drain extension. A 10 ps/stage dela is recorded at 85 K from a 0.08 pm channel ring osciiator, which is the fastest switching speed ever reported for any silicon device. The delay at room temperature is 13 ps/stage. Unity-current-gain frequency cutoK7 vr) of a 0.09 pm channel device are 119 GHz at 85 K and 93 GHz at 300 K. Record high saturation transconductances, 1040 mS/mm at 85 K and 740 mSlmm at 300 K , are obtained from a 0.05 pm channel device. Good subthreshold characteristics arc achieved for 0.1 pm channel devices.

2010 Symposium on VLSI Circuits, 2010

POWER7 Microprocessor Architecture 1 • Eight cores and their associated L2 and L3 caches connecte... more POWER7 Microprocessor Architecture 1 • Eight cores and their associated L2 and L3 caches connected to each other through an asynchronous, memory coherent bus • Each core can run at its own speed • Core frequency is centrally managed to optimize for performance / power dissipation / etc.

Recent advances in fabricating, measuring, and modeling of top-gated graphene FETs for high-frequ... more Recent advances in fabricating, measuring, and modeling of top-gated graphene FETs for high-frequency electronics are reviewed. By improving the oxide deposition process and reducing series resistance, an intrinsic cutoff frequency as high as 50 GHz is achieved in a 350-nm-gate graphene FET at a drain bias of 0.8 V. This f T value is the highest frequency reported to date for any graphene transistor, and it also exceeds that of Si MOSFETs at the same gate length, illustrating the potential of graphene for RF applications.

2011 International Reliability Physics Symposium, 2011

Ring oscillator (RO) structures that separate NBTI and PBTI effects are implemented in a high-k m... more Ring oscillator (RO) structures that separate NBTI and PBTI effects are implemented in a high-k metal gate technology. The measurement results clearly show significant RO frequency degradation from PBTI as well as NBTI. For comparison, RO structures with the same principle are also implemented in a SiO 2 /poly-gate technology, where PBTI is negligible. Experimental results show noticeable frequency degradation under NBTI-only stress mode but negligible degradation under PBTI-only mode, which illustrates the validity of the proposed principle and structures.

2011 International Electron Devices Meeting, 2011

Wafer-scale graphene devices processed entirely in a standard 200 mm silicon fab are demonstrated... more Wafer-scale graphene devices processed entirely in a standard 200 mm silicon fab are demonstrated for the first time. New embedded gate structures enable full saturation of the drain current in graphene FETs with sub-µm channels, resulting in high intrinsic voltage gain. In addition, passive devices were monolithically integrated with graphene transistors to form the first GHz-range graphene IC using large-scale CVD graphene. The demonstration of high performance graphene FETs and IC fabricated using a 200 mm platform is a major step in transitioning this promising material from a scientific curiosity into a real technology.

Science, 2011

Components such as inductors were fabricated alongside graphene transistors to create integrated ... more Components such as inductors were fabricated alongside graphene transistors to create integrated radio-frequency mixers.

Science, 2010

The maximum switching frequency of these devices exceeds that of silicon transistors with similar... more The maximum switching frequency of these devices exceeds that of silicon transistors with similar gate-electrode dimensions.

Nature Communications, 2014

Graphene has attracted much interest as a future channel material in radio frequency electronics ... more Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6 mm 2 area and fabricated on 200 mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal-oxide-semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal.

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)

A novel vertical bipolar transistor on SOI is proposed and demonstrated. The SOI silicon layer th... more A novel vertical bipolar transistor on SOI is proposed and demonstrated. The SOI silicon layer thickness is comparable to that used in SOI CMOS, and no subcollector layer or deep trench isolation are required. Simulated device characteristics are shown. The transistor is demonstrated in a polysilicon-emitter SiGe-base npn implementation on SOI with a 140-nm silicon layer. The fabricated npn bipolar transistors exhibit a BVceo of 4.2V and a peak f T of over 60GHz.

Extended Abstracts of the 2003 International Conference on Solid State Devices and Materials, 2003

2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, 2010

In this work, we studied current transport in mono-, biand tri-layer graphene. We find that both ... more In this work, we studied current transport in mono-, biand tri-layer graphene. We find that both the temperature and carrier density dependencies in monolayer and bi-/tri-layers are diametrically opposite. These difference can be understood by the different density-of-states and the additional screening of the electrical field of the substrate surface polar phonons in bi-layer/tri-layer graphenes. We also find that silicon nitride can provide uniform coverage of graphene in field-effect transistors while preserving the channel mobility. Using this insulator, we studied field-induced band-gap or band-overlap in graphene with various numbers of layers.

2011 International Electron Devices Meeting, 2011

High-frequency performance of graphene field-effect transistors (GFETs) with boron-nitride gate d... more High-frequency performance of graphene field-effect transistors (GFETs) with boron-nitride gate dielectrics is investigated. Devices show saturating IV characteristics and f max values as high as 34 GHz at 600-nm channel length. Bias dependence of f T and f max and the effect of the ambipolar channel on transconductance and output resistance are also examined.

Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena, 2010

Up to two layers of epitaxial graphene have been grown on the Si-face of 2 in. SiC wafers exhibit... more Up to two layers of epitaxial graphene have been grown on the Si-face of 2 in. SiC wafers exhibiting room-temperature Hall mobilities up to 2750 cm2 V−1 s−1, measured from ungated, large, 160×200 μm2 Hall bars, and up to 4000 cm2 V−1 s−1, from top-gated, small, 1×1.5 μm2 Hall bars. The growth process involved a combination of a cleaning step of the SiC in a Si-containing gas, followed by an annealing step in argon for epitaxial graphene formation. The structure and morphology of this graphene has been characterized using atomic force microscopy, high resolution transmission electron microscopy, and Raman spectroscopy. Furthermore, top-gated radio frequency field-effect transistors (rf-FETs) with a peak cutoff frequency fT of 100 GHz for a gate length of 240 nm were fabricated using epitaxial graphene grown on the Si-face of SiC that exhibited Hall mobilities up to 1450 cm2 V−1 s−1 from ungated Hall bars and 1575 cm2 V−1 s−1 from top-gated ones. This is by far the highest cutoff freq...

IEEE Journal of Solid-State Circuits, 2008

This paper presents an on-chip characterization method for random variation in minimum sized devi... more This paper presents an on-chip characterization method for random variation in minimum sized devices in nanometer technologies, using a sense amplifier-based test circuit. Instead of analog current measurements required in conventional techniques, the presented circuit operates using digital voltage measurements. Simulations of the test structure using predictive 70 nm and hardware based 0.13 m CMOS technologies show good accuracy (error 5%-10%) in the prediction of random variation even in the presence of systematic variations. A test chip is fabricated in 0.13 m bulk CMOS technology and measured to demonstrate the operation of the test structure.

2010 International Electron Devices Meeting, 2010

International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003., 2003

The effects of gate structure design on RF performance of strained-Si/SiGe nMODFETs are studied u... more The effects of gate structure design on RF performance of strained-Si/SiGe nMODFETs are studied using device simulation and experiments. It is found that while gate resistance only affects f max , fringing gate capacitance can have a significant impact on both f T and f max , indicating that the physical gate structure has to be optimized for any specific application. The experiments suggest that low-κ material is needed as sidewall spacer (if any) and passivation for reducing fringing gate capacitance. Furthermore, the simulations show that if low gate resistance can be achieved by using a multi-finger geometry, a rectangular-shaped gate should be used in order to reduce fringing gate capacitance. If not, a T-gate should be used to reduce gate resistance for high f max .

Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)

A "System on a Chip" is described, which integrates 16Mbits of DRAM, digital logic, SRAM, three P... more A "System on a Chip" is described, which integrates 16Mbits of DRAM, digital logic, SRAM, three PLLs, and a triple video Digital-to-analog converter in a 0.5 micron CMOS DRAM process. Application Specific Integrated Circuit (ASIC) techniques are employed, using multiple DRAM macros with Built-in Self Test (BIST), full Level-Sensitive Scan Design (LSSD) logic, and externally accessible analog circuitry. Issues regarding functional debugging, DRAM macro isolation and low cost manufacturing test using only a logic tester are described.

23rd IEEE VLSI Test Symposium (VTS'05)

This paper presents the design of an on-chip spectrum analyzer. A novel architecture is used to m... more This paper presents the design of an on-chip spectrum analyzer. A novel architecture is used to mitigate the problems encountered in trying to implement architectures employed in conventional stand-alone instruments on a chip. Specifically, it makes use of a very-low IF architecture, which leads to a highly compact design, that can be used for measuring the frequency content of high frequency on-chip signals. The architecture and design considerations along with an implementation in a 0.18 µm CMOS process is described. The design takes up an area of approximately 0.384 mm 2 with a simulated frequency range of 33 MHz to 3 GHz and a dynamic range of 60 dB.

Symposium on VLSI Technology, 1993

Very hi h performance 0.1 pm nMOSFETs are fabricated witf 3.5 nm gate oxide and shallow arsenic/b... more Very hi h performance 0.1 pm nMOSFETs are fabricated witf 3.5 nm gate oxide and shallow arsenic/boron (halo) source-drain extension. A 10 ps/stage dela is recorded at 85 K from a 0.08 pm channel ring osciiator, which is the fastest switching speed ever reported for any silicon device. The delay at room temperature is 13 ps/stage. Unity-current-gain frequency cutoK7 vr) of a 0.09 pm channel device are 119 GHz at 85 K and 93 GHz at 300 K. Record high saturation transconductances, 1040 mS/mm at 85 K and 740 mSlmm at 300 K , are obtained from a 0.05 pm channel device. Good subthreshold characteristics arc achieved for 0.1 pm channel devices.

2010 Symposium on VLSI Circuits, 2010

POWER7 Microprocessor Architecture 1 • Eight cores and their associated L2 and L3 caches connecte... more POWER7 Microprocessor Architecture 1 • Eight cores and their associated L2 and L3 caches connected to each other through an asynchronous, memory coherent bus • Each core can run at its own speed • Core frequency is centrally managed to optimize for performance / power dissipation / etc.

Recent advances in fabricating, measuring, and modeling of top-gated graphene FETs for high-frequ... more Recent advances in fabricating, measuring, and modeling of top-gated graphene FETs for high-frequency electronics are reviewed. By improving the oxide deposition process and reducing series resistance, an intrinsic cutoff frequency as high as 50 GHz is achieved in a 350-nm-gate graphene FET at a drain bias of 0.8 V. This f T value is the highest frequency reported to date for any graphene transistor, and it also exceeds that of Si MOSFETs at the same gate length, illustrating the potential of graphene for RF applications.

2011 International Reliability Physics Symposium, 2011

Ring oscillator (RO) structures that separate NBTI and PBTI effects are implemented in a high-k m... more Ring oscillator (RO) structures that separate NBTI and PBTI effects are implemented in a high-k metal gate technology. The measurement results clearly show significant RO frequency degradation from PBTI as well as NBTI. For comparison, RO structures with the same principle are also implemented in a SiO 2 /poly-gate technology, where PBTI is negligible. Experimental results show noticeable frequency degradation under NBTI-only stress mode but negligible degradation under PBTI-only mode, which illustrates the validity of the proposed principle and structures.

2011 International Electron Devices Meeting, 2011

Wafer-scale graphene devices processed entirely in a standard 200 mm silicon fab are demonstrated... more Wafer-scale graphene devices processed entirely in a standard 200 mm silicon fab are demonstrated for the first time. New embedded gate structures enable full saturation of the drain current in graphene FETs with sub-µm channels, resulting in high intrinsic voltage gain. In addition, passive devices were monolithically integrated with graphene transistors to form the first GHz-range graphene IC using large-scale CVD graphene. The demonstration of high performance graphene FETs and IC fabricated using a 200 mm platform is a major step in transitioning this promising material from a scientific curiosity into a real technology.

Science, 2011

Components such as inductors were fabricated alongside graphene transistors to create integrated ... more Components such as inductors were fabricated alongside graphene transistors to create integrated radio-frequency mixers.

Science, 2010

The maximum switching frequency of these devices exceeds that of silicon transistors with similar... more The maximum switching frequency of these devices exceeds that of silicon transistors with similar gate-electrode dimensions.

Nature Communications, 2014

Graphene has attracted much interest as a future channel material in radio frequency electronics ... more Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6 mm 2 area and fabricated on 200 mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal-oxide-semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal.