pallavi darji - Academia.edu (original) (raw)
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Papers by pallavi darji
Communications in computer and information science, 2023
2022 IEEE Region 10 Symposium (TENSYMP), Jul 1, 2022
Communications in Computer and Information Science, 2017
High resolution DACs require large transistors to obtain the desired accuracy according to the Pe... more High resolution DACs require large transistors to obtain the desired accuracy according to the Pelgrom model [1], which increases the area drastically. To overcome this area accuracy trade off, several calibration techniques were investigated. This paper presents a modified self calibration technique for current-steering (CS) digital-to-analog converters (DACs). In the digital calibration technique calibrating DACs (CALDACs) are connected across each bit, which requires calibration. High resolution CALDAC increases the accuracy at a cost of increment in the area. To overcome this problem, this technique is slightly modified. Instead of using CALDAC of 6 or 8 bits across each bit, here a single CALDAC is used to calibrate each bit, and its equivalent calibrated value in terms of analog voltage is stored across the capacitor (instead of within SRAM memory in digital form), which is connected in the place of CALDAC by using an extra-auxiliary transistor. MOSFET as a switch is used for simultaneous switching and to hold the correct voltage after turning off switches, injection nulling switch type track and hold circuit is used. To demonstrate this technique, a 10-bit binary-weighted CS DAC is implemented in a 0.18 \(\upmu \)m CMOS process. With worst-case process parameter variations, simulated integral and differential nonlinearities of the calibrated DAC are less than 0.32 LSB.
Circuits, Systems, and Signal Processing, 2015
This paper reports the post-layout dynamic performance of a novel calibration technique for curre... more This paper reports the post-layout dynamic performance of a novel calibration technique for current-steering digital-to-analog converter that was proposed previously. This technique not only improves the linearity, but it does so with low power as well as a very low area. It uses an analog feedback loop consisting of four transistors to calibrate each bit of the DAC, and the same feedback circuit is used for all the bits, thus significantly saving the chip area. Layout of the 10-bit calibrated CS DAC circuit was done in a 180-nm technology; the total area of the DAC and the calibration circuit together was 0.16 mm 2. Simulation results show that the spurious free dynamic range is 62 dB for signals of 1 MHz at a sampling frequency of 100 MS/s.
Proceedings of the International Conference on Advances in Computer Science and Electronics Engineering, 2012
This paper presents a novel Current Steering Digital to Analog Converter architecture to reduce a... more This paper presents a novel Current Steering Digital to Analog Converter architecture to reduce area as well as power dissipation. The current cells of conventional binary weighted architecture require larger size of transistors for MSBs. In this paper, same sized current cell transistors for MSBs as that of LSBs and a current mirror circuit is used between the load and MSBs to provide necessary higher current. Here, 6-bit CS-DAC is simulated. The area of this proposed CS-DAC has decreased by about 12% and power dissipation by about 50% in comparison with a conventional Binary architecture.
Communications in computer and information science, 2023
2022 IEEE Region 10 Symposium (TENSYMP), Jul 1, 2022
Communications in Computer and Information Science, 2017
High resolution DACs require large transistors to obtain the desired accuracy according to the Pe... more High resolution DACs require large transistors to obtain the desired accuracy according to the Pelgrom model [1], which increases the area drastically. To overcome this area accuracy trade off, several calibration techniques were investigated. This paper presents a modified self calibration technique for current-steering (CS) digital-to-analog converters (DACs). In the digital calibration technique calibrating DACs (CALDACs) are connected across each bit, which requires calibration. High resolution CALDAC increases the accuracy at a cost of increment in the area. To overcome this problem, this technique is slightly modified. Instead of using CALDAC of 6 or 8 bits across each bit, here a single CALDAC is used to calibrate each bit, and its equivalent calibrated value in terms of analog voltage is stored across the capacitor (instead of within SRAM memory in digital form), which is connected in the place of CALDAC by using an extra-auxiliary transistor. MOSFET as a switch is used for simultaneous switching and to hold the correct voltage after turning off switches, injection nulling switch type track and hold circuit is used. To demonstrate this technique, a 10-bit binary-weighted CS DAC is implemented in a 0.18 \(\upmu \)m CMOS process. With worst-case process parameter variations, simulated integral and differential nonlinearities of the calibrated DAC are less than 0.32 LSB.
Circuits, Systems, and Signal Processing, 2015
This paper reports the post-layout dynamic performance of a novel calibration technique for curre... more This paper reports the post-layout dynamic performance of a novel calibration technique for current-steering digital-to-analog converter that was proposed previously. This technique not only improves the linearity, but it does so with low power as well as a very low area. It uses an analog feedback loop consisting of four transistors to calibrate each bit of the DAC, and the same feedback circuit is used for all the bits, thus significantly saving the chip area. Layout of the 10-bit calibrated CS DAC circuit was done in a 180-nm technology; the total area of the DAC and the calibration circuit together was 0.16 mm 2. Simulation results show that the spurious free dynamic range is 62 dB for signals of 1 MHz at a sampling frequency of 100 MS/s.
Proceedings of the International Conference on Advances in Computer Science and Electronics Engineering, 2012
This paper presents a novel Current Steering Digital to Analog Converter architecture to reduce a... more This paper presents a novel Current Steering Digital to Analog Converter architecture to reduce area as well as power dissipation. The current cells of conventional binary weighted architecture require larger size of transistors for MSBs. In this paper, same sized current cell transistors for MSBs as that of LSBs and a current mirror circuit is used between the load and MSBs to provide necessary higher current. Here, 6-bit CS-DAC is simulated. The area of this proposed CS-DAC has decreased by about 12% and power dissipation by about 50% in comparison with a conventional Binary architecture.