vartika pandey - Academia.edu (original) (raw)
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Papers by vartika pandey
International Journal of Innovative Technology and Exploring Engineering, 2020
A Process parameter variation has increasing, which results unpredictable device behaviour, due t... more A Process parameter variation has increasing, which results unpredictable device behaviour, due to occurrence of deep submicron CMOS technology. As the time passage this issue is exasperated by low power requirements which are approaching transistor operation into sub threshold regime. Principally for portable devices efficient, capable and process variation amiable memory is the most demandable in the market. In designing of low power memories, leakage power is observant parameter to design low power devices, because leakage power plays a dominant role in the total power utilization of the devices. In this paper, simple 6T SRAM formed with memristor has compared with the technique based 6T SRAM for the various parameters like total power and leakage power
2020 Fourth World Conference on Smart Trends in Systems, Security and Sustainability (WorldS4), 2020
The main focus of this article is the reliability and aging of the 6T (SRAM) Static random access... more The main focus of this article is the reliability and aging of the 6T (SRAM) Static random access memories. From many days of the SRAM circuit have been used, so consider its reliability and aging factor. In this paper reliability and aging are performed under the parameters of (HCI), (NBTI) and (PBTI). Fidelity is an impetus creation in the SRAM-consuming cycle because it expands the footprint of every specific MOSFET and corral in relation to the source. With more robust findings, reliability has displayed thater affect of a individual transistor activate to poor performance of the 6T SRAM and ultimately leads to damage
2013 7th International Conference on Intelligent Systems and Control, 2013
ABSTRACT This paper describes low power and high performance comparator with hysteresis effect at... more ABSTRACT This paper describes low power and high performance comparator with hysteresis effect at 45 nm technology. Simulation of Comparator with hysteresis as compared same configuration without hysteresis provides leakage power 4.867 µW. Comparator is to be designed propose to perform comparison of voltage at two terminals with reference voltage 500 mV, since the input are balanced. Leakage power performance optimization of comparator using Multi-threshold (MCTMOS) logic. Leakage power is achieved to optimal value of 73.03 femto watt. Delay is reduced to 12% with hysteresis in comparison to without hysteresis. Voltage gain is higher up to 40% as compared with comparator (without hysteresis). Offset value is reduced to 80% with hysteresis effect. Inverter output buffer stage followed the decision stage is reduces the offset error.
International Journal of Innovative Technology and Exploring Engineering, 2020
A Process parameter variation has increasing, which results unpredictable device behaviour, due t... more A Process parameter variation has increasing, which results unpredictable device behaviour, due to occurrence of deep submicron CMOS technology. As the time passage this issue is exasperated by low power requirements which are approaching transistor operation into sub threshold regime. Principally for portable devices efficient, capable and process variation amiable memory is the most demandable in the market. In designing of low power memories, leakage power is observant parameter to design low power devices, because leakage power plays a dominant role in the total power utilization of the devices. In this paper, simple 6T SRAM formed with memristor has compared with the technique based 6T SRAM for the various parameters like total power and leakage power
2020 Fourth World Conference on Smart Trends in Systems, Security and Sustainability (WorldS4), 2020
The main focus of this article is the reliability and aging of the 6T (SRAM) Static random access... more The main focus of this article is the reliability and aging of the 6T (SRAM) Static random access memories. From many days of the SRAM circuit have been used, so consider its reliability and aging factor. In this paper reliability and aging are performed under the parameters of (HCI), (NBTI) and (PBTI). Fidelity is an impetus creation in the SRAM-consuming cycle because it expands the footprint of every specific MOSFET and corral in relation to the source. With more robust findings, reliability has displayed thater affect of a individual transistor activate to poor performance of the 6T SRAM and ultimately leads to damage
2013 7th International Conference on Intelligent Systems and Control, 2013
ABSTRACT This paper describes low power and high performance comparator with hysteresis effect at... more ABSTRACT This paper describes low power and high performance comparator with hysteresis effect at 45 nm technology. Simulation of Comparator with hysteresis as compared same configuration without hysteresis provides leakage power 4.867 µW. Comparator is to be designed propose to perform comparison of voltage at two terminals with reference voltage 500 mV, since the input are balanced. Leakage power performance optimization of comparator using Multi-threshold (MCTMOS) logic. Leakage power is achieved to optimal value of 73.03 femto watt. Delay is reduced to 12% with hysteresis in comparison to without hysteresis. Voltage gain is higher up to 40% as compared with comparator (without hysteresis). Offset value is reduced to 80% with hysteresis effect. Inverter output buffer stage followed the decision stage is reduces the offset error.