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Papers by sriram venkateswaran

The challenge of extending Moore's Law past the physical limits of the present semiconductor tech... more The challenge of extending Moore's Law past the physical limits of the present semiconductor technology calls for novel innovations. Several novel nanotechnologies are being proposed as an alternative to their CMOS counterparts, with nanowire crossbar being one of the most promising paradigms. Quite recently, a new promising clock-free architecture, called the Asynchronous Crossbar Architecture has been proposed to enhance the manufacturability and to improve the robustness of digital circuits by removing various timing related failure modes. Even though the proposed clock-free architecture offers several merits, it is not free from the high defect rates induced due to nondeterministic nanoscale assembly. In this work, a unique Functional Test Algorithm (FTA) has been proposed and validated to test for manufacturing defects in this architecture. The proposed Functional Test Algorithm is aimed at reducing the testing overhead in terms of the time and space complexity associated with the existing sequential test scheme. In addition, it is designed to provide high fault coverage and excellent fault-tolerance via post-reconfiguration. This test scheme can be effectively used to assure true functionality of any threshold gate realized on a given PGMB. The main motivation behind this research is to propose a comprehensive test scheme which can achieve sufficiently high test coverage with acceptable test overhead. This test algorithm is a significant effort towards viable nanoscale computation. This work has been organized into three papers, explaining the proposed algorithm, demonstrating its working, describing the achievable replacement schemes using the proposed tool and providing a performance evaluation metric specifically proposed to evaluate the functional test algorithm. v ACKNOWLEDGEMENTS First and foremost, I would like to thank Almighty God for providing me with all the good health, strength and knowledge to complete my thesis and masters. I would like to express sincere gratitude and heartfelt thanks to my advisor Dr. Minsu Choi for his guidance, encouragement and invaluable contributions throughout my graduate study as well as in completing this research. I would also like to thank him for providing me with financial support during my master's study. To my committee members, Dr. Sahra Sedigh and Dr. Theodore McCracken, I extend my deepest appreciation and thanks for their time and effort in serving as committee members and reviewing this dissertation. My sincere thanks to Dr. V A Samaranayake of Mathematics and Statistics department for his important inputs. Special thanks to Ravi Bonam and Shikha Chaudhary, senior research members of Dr.Choi's research group for their help and ideas. Thanks go to my friends and roommates for all the happy times and memorable moments we shared. Lastly, but most importantly, I am indebted to my parents, my mother aunt for their unparallel love and patience with me during my endeavors. Without special support and motivation from my uncles, aunt and love from my brothers, Srihari, Varun, Karthik and young sister Vaishnavi, grandparents and all my close relatives and friends back in India, I would not have been able to reach this stage of life. vi

2009 IEEE Intrumentation and Measurement Technology Conference, 2009

The recently proposed asynchronous nanowire clock-free crossbar architecture is envisioned to enh... more The recently proposed asynchronous nanowire clock-free crossbar architecture is envisioned to enhance the manufacturability and to improve the robustness of digital circuits by removing various timing-related failure modes. Even though the proposed clock-free architecture has numerous merits over its clocked counterpart, it is still not free from high defect rates inherently induced by nondeterministic nanoscale assembly. In order to address this issue, a novel functional test scheme for validating threshold gates on programmable gate macro blocks (PGMB) has been proposed. The main aim of this paper is to present a test algorithm that can be used to identify manufacturing defects at programmable locations on a PGMB. In addition, this paper also presents several replacement and re-arrangement schemes to enable true realization of threshold gates. Specific figures of merits have also been coined to quantify the performance of the algorithm. This is a very significant step towards efficient defect testing since the earlier existing test scheme failed to provide any significant breakthrough as far as testing mechanisms were concerned. The proposed approach tests only the crosspoints programmed as ON state using input patterns unique to the given threshold gate macro. The proposed scheme helps achieve correct programmability with minimal test overhead. This test scheme can be used to assure the true functionality of any threshold gate on a given PGMB. The proposed scheme is anticipated to provide high fault coverage and excellent fault tolerance. These findings have been backed by parametric simulation results using MATLAB.

2008 8th IEEE Conference on Nanotechnology, 2008

An asynchronous nanowire crossbar architecture has been recently proposed to eliminate the clock ... more An asynchronous nanowire crossbar architecture has been recently proposed to eliminate the clock distribution network from conventional clocked counterpart. The proposed clock-free architecture is envisioned to enhance the manufacturability with simpler periodic structure and to improve the robustness by removing various timing-related failure modes. Even though the proposed clock-free architecture has numerous merits over its clocked counterpart, it is still not free from high defect rates induced by nondeterministic nanoscale assembly. In order to address this issue, our research team has been working on developing test schemes for effective mapping of threshold gates onto Programmable Gate Macro Blocks (PGMB). We have come up with a novel functional test approach which uses prioritized input tuples to effectively stimulate coinciding defects in configured PGMB. Numerous preliminary plots and results obtained till date prove that this scheme can be used to achieve high test efficiency for any threshold gate. The main motivation behind this research is to propose a comprehensive test scheme which can achieve high enough test coverage with acceptable test overhead. Parametric simulation results using MATLAB have been used to show potential performance of this testing scheme.

IET Computers & Digital Techniques, 2012

The recently proposed asynchronous nanowire crossbar architecture is envisioned to enhance the ma... more The recently proposed asynchronous nanowire crossbar architecture is envisioned to enhance the manufacturability and robustness of nanowire crossbar-based configurable digital circuits by removing various timing-related failure modes. Even though the proposed clock-free nanowire crossbar architecture has numerous technical merits over its clocked counterparts, it is still subject to high defect rates inherently induced by the non-deterministic nanoscale assembly of nanowire crossbars. In order to address this issue, a novel functional testing scheme has been proposed to validate threshold gates configured on programmable gate macro blocks (PGMB). The proposed approach selectively tests the crosspoints programmed as ON-state using test vectors tailored to the given threshold gate macro and its functionality. Therefore high-fault coverage can be achieved at significantly reduced test overhead. Also, numerous replacement and reconfiguration schemes have been proposed based on the proposed functional testing scheme to repair configured PGMBs that are partially faulty by locating incorrectly programmed crosspoints and replacing them with defect-free spares. Specific figures of merit have also been coined to quantify the performance of the proposed testing and reconfiguration algorithms. These findings have been extensively validated by a series of parametric simulations.

Cutting Edge Nanotechnology, 2010

The challenge of extending Moore's Law past the physical limits of the present semiconductor tech... more The challenge of extending Moore's Law past the physical limits of the present semiconductor technology calls for novel innovations. Several novel nanotechnologies are being proposed as an alternative to their CMOS counterparts, with nanowire crossbar being one of the most promising paradigms. Quite recently, a new promising clock-free architecture, called the Asynchronous Crossbar Architecture has been proposed to enhance the manufacturability and to improve the robustness of digital circuits by removing various timing related failure modes. Even though the proposed clock-free architecture offers several merits, it is not free from the high defect rates induced due to nondeterministic nanoscale assembly. In this work, a unique Functional Test Algorithm (FTA) has been proposed and validated to test for manufacturing defects in this architecture. The proposed Functional Test Algorithm is aimed at reducing the testing overhead in terms of the time and space complexity associated with the existing sequential test scheme. In addition, it is designed to provide high fault coverage and excellent fault-tolerance via post-reconfiguration. This test scheme can be effectively used to assure true functionality of any threshold gate realized on a given PGMB. The main motivation behind this research is to propose a comprehensive test scheme which can achieve sufficiently high test coverage with acceptable test overhead. This test algorithm is a significant effort towards viable nanoscale computation. This work has been organized into three papers, explaining the proposed algorithm, demonstrating its working, describing the achievable replacement schemes using the proposed tool and providing a performance evaluation metric specifically proposed to evaluate the functional test algorithm. v ACKNOWLEDGEMENTS First and foremost, I would like to thank Almighty God for providing me with all the good health, strength and knowledge to complete my thesis and masters. I would like to express sincere gratitude and heartfelt thanks to my advisor Dr. Minsu Choi for his guidance, encouragement and invaluable contributions throughout my graduate study as well as in completing this research. I would also like to thank him for providing me with financial support during my master's study. To my committee members, Dr. Sahra Sedigh and Dr. Theodore McCracken, I extend my deepest appreciation and thanks for their time and effort in serving as committee members and reviewing this dissertation. My sincere thanks to Dr. V A Samaranayake of Mathematics and Statistics department for his important inputs. Special thanks to Ravi Bonam and Shikha Chaudhary, senior research members of Dr.Choi's research group for their help and ideas. Thanks go to my friends and roommates for all the happy times and memorable moments we shared. Lastly, but most importantly, I am indebted to my parents, my mother aunt for their unparallel love and patience with me during my endeavors. Without special support and motivation from my uncles, aunt and love from my brothers, Srihari, Varun, Karthik and young sister Vaishnavi, grandparents and all my close relatives and friends back in India, I would not have been able to reach this stage of life. vi

2009 IEEE Intrumentation and Measurement Technology Conference, 2009

The recently proposed asynchronous nanowire clock-free crossbar architecture is envisioned to enh... more The recently proposed asynchronous nanowire clock-free crossbar architecture is envisioned to enhance the manufacturability and to improve the robustness of digital circuits by removing various timing-related failure modes. Even though the proposed clock-free architecture has numerous merits over its clocked counterpart, it is still not free from high defect rates inherently induced by nondeterministic nanoscale assembly. In order to address this issue, a novel functional test scheme for validating threshold gates on programmable gate macro blocks (PGMB) has been proposed. The main aim of this paper is to present a test algorithm that can be used to identify manufacturing defects at programmable locations on a PGMB. In addition, this paper also presents several replacement and re-arrangement schemes to enable true realization of threshold gates. Specific figures of merits have also been coined to quantify the performance of the algorithm. This is a very significant step towards efficient defect testing since the earlier existing test scheme failed to provide any significant breakthrough as far as testing mechanisms were concerned. The proposed approach tests only the crosspoints programmed as ON state using input patterns unique to the given threshold gate macro. The proposed scheme helps achieve correct programmability with minimal test overhead. This test scheme can be used to assure the true functionality of any threshold gate on a given PGMB. The proposed scheme is anticipated to provide high fault coverage and excellent fault tolerance. These findings have been backed by parametric simulation results using MATLAB.

2008 8th IEEE Conference on Nanotechnology, 2008

An asynchronous nanowire crossbar architecture has been recently proposed to eliminate the clock ... more An asynchronous nanowire crossbar architecture has been recently proposed to eliminate the clock distribution network from conventional clocked counterpart. The proposed clock-free architecture is envisioned to enhance the manufacturability with simpler periodic structure and to improve the robustness by removing various timing-related failure modes. Even though the proposed clock-free architecture has numerous merits over its clocked counterpart, it is still not free from high defect rates induced by nondeterministic nanoscale assembly. In order to address this issue, our research team has been working on developing test schemes for effective mapping of threshold gates onto Programmable Gate Macro Blocks (PGMB). We have come up with a novel functional test approach which uses prioritized input tuples to effectively stimulate coinciding defects in configured PGMB. Numerous preliminary plots and results obtained till date prove that this scheme can be used to achieve high test efficiency for any threshold gate. The main motivation behind this research is to propose a comprehensive test scheme which can achieve high enough test coverage with acceptable test overhead. Parametric simulation results using MATLAB have been used to show potential performance of this testing scheme.

IET Computers & Digital Techniques, 2012

The recently proposed asynchronous nanowire crossbar architecture is envisioned to enhance the ma... more The recently proposed asynchronous nanowire crossbar architecture is envisioned to enhance the manufacturability and robustness of nanowire crossbar-based configurable digital circuits by removing various timing-related failure modes. Even though the proposed clock-free nanowire crossbar architecture has numerous technical merits over its clocked counterparts, it is still subject to high defect rates inherently induced by the non-deterministic nanoscale assembly of nanowire crossbars. In order to address this issue, a novel functional testing scheme has been proposed to validate threshold gates configured on programmable gate macro blocks (PGMB). The proposed approach selectively tests the crosspoints programmed as ON-state using test vectors tailored to the given threshold gate macro and its functionality. Therefore high-fault coverage can be achieved at significantly reduced test overhead. Also, numerous replacement and reconfiguration schemes have been proposed based on the proposed functional testing scheme to repair configured PGMBs that are partially faulty by locating incorrectly programmed crosspoints and replacing them with defect-free spares. Specific figures of merit have also been coined to quantify the performance of the proposed testing and reconfiguration algorithms. These findings have been extensively validated by a series of parametric simulations.

Cutting Edge Nanotechnology, 2010