vilas patil - Academia.edu (original) (raw)
Papers by vilas patil
Current Applied Physics, 2021
The HF treatment removes the native oxide and lays behind the dangling bonds over the Si surface ... more The HF treatment removes the native oxide and lays behind the dangling bonds over the Si surface which causes the increment in density of interface traps (D it) through the direct deposition of high-k dielectric on Si. Here, we propose the facile method for reduction of interface traps and improvement in barrier height with the (NH 4) 2 S treatment on Al 2 O 3 /Si interfaces, which can be used as the base for the non-volatile memory device. The AFM was used to optimize the treatment time and surface properties, while XPS measurements were carried out to study the interface and extract the barrier height (Φ B). The short period of 20 s treatment shows the improvement in the barrier height (1.02 eV), while the one order reduction in the D it (0.84 × 10 12 cm 2 /eV) of sulfur passivated Al/Al 2 O 3 /Si MOS device. The results indicate the favorable passivation of the dangling bonds over the Si surfaces covered by sulfur atoms.
Current Applied Physics, 2021
The HF treatment removes the native oxide and lays behind the dangling bonds over the Si surface ... more The HF treatment removes the native oxide and lays behind the dangling bonds over the Si surface which causes the increment in density of interface traps (D it) through the direct deposition of high-k dielectric on Si. Here, we propose the facile method for reduction of interface traps and improvement in barrier height with the (NH 4) 2 S treatment on Al 2 O 3 /Si interfaces, which can be used as the base for the non-volatile memory device. The AFM was used to optimize the treatment time and surface properties, while XPS measurements were carried out to study the interface and extract the barrier height (Φ B). The short period of 20 s treatment shows the improvement in the barrier height (1.02 eV), while the one order reduction in the D it (0.84 × 10 12 cm 2 /eV) of sulfur passivated Al/Al 2 O 3 /Si MOS device. The results indicate the favorable passivation of the dangling bonds over the Si surfaces covered by sulfur atoms.
ECS Journal of Solid State Science and Technology, 2020
Journal of Materials Science: Materials in Electronics, 2020
We report the effect of variation of the channel width-to-length aspect ratio on the negative bia... more We report the effect of variation of the channel width-to-length aspect ratio on the negative bias stress instability and the impact of the source/drain contact resistance on the electrical properties of amorphous-InGaZnO (IGZO) thin-film transistor (TFT) arrays. An asymmetric degradation of the threshold voltage (V th) was observed over a wide range of negative stress bias in the IGZO TFT arrays. The lowest ∆V th of 0.8 V and good stability with an increase in stress time were observed for the array having the channel aspect ratio of ~ 1.5, whereas the highest ∆V th of 5.2 V was observed for the array having the channel aspect ratio of ~ 2.5. The drain-induced barrier lowering (DIBL) mechanism and the transmission line method (TLM) were used to investigate this abnormal degradation. The maximum DIBL of 50.2 mV/V was calculated for the array having a channel width/length of 4.4/11 μm. Application of the TLM revealed a channel resistance of 10.4 kΩ μm at a small gate bias of 0.5 V. Degradation of the electrical properties was observed for the array having an aspect ratio of 2.5 owing to poor ohmic contact with the channel. This investigation suggests that proper selection of the aspect ratio is important in the design of small-scale TFT arrays, as it can help to reduce the degradation of the electrical properties at a smaller dimension. Short-channel effects such as electron trapping and parasitic resistances can be minimized via improvement of the bias stress instability by use of a width-to-length aspect ratio of ~ 1.5. The findings in this report are beneficial for designing ultra-high-definition active-matrix displays.
Solid-State Electronics, 2020
The lower mobility for p-type Ge based is always an issue due to slow traps generation at the int... more The lower mobility for p-type Ge based is always an issue due to slow traps generation at the interface of the metal oxide semiconductor (MOS) device which designates the defects in films generated during the deposition process. One of the effective ways to reduce this slow traps generation is to perform post deposition annealing (PDA) at a certain temperature. However, the selection of proper annealing temperature is the key to reduce defects without damaging the film quality. The effect of different PDA temperatures on the slow traps generation mechanism in the GeON passivated Ge MOS device was examined in this work. The XPS spectra show the stable formation of GeON over Ge, while HRTEM does not show any effect of PDA at the interface of GeON/Ge. The slow trap density (ΔN st) in HfO 2 /GeON/Ge interface annealed at different temperatures was evaluated from the hysteresis curve of C-V sweep as the function of the effective oxide field. The lowest ΔN st (4.01 × 10 12 cm −2) was observed for the PDA temperature for 400 ℃. While, ΔN st increased slightly after PDA at 450 ℃. The work suggests that PDA at lower temperatures is essential to realize the high quality interface with lower interface trap density, enhanced mobility and lower CET in Ge based MOS devices. Further, it also helps to reduce the slow traps generations at the interface.
Semiconductor Science and Technology, 2018
The ZrO2/La2O3 bilayer structure has been formed on Si by using atomic layer deposition system. T... more The ZrO2/La2O3 bilayer structure has been formed on Si by using atomic layer deposition system. The ZrO2/La2O3 (ZLS) bilayer was swapped to La2O3/ZrO2 (LZS) on Si and the interface properties were investigated. The chemical compositions of deposited thin films were studied by using XPS, while surface properties were investigated by means of AFM. The shift in binding energies of both gate stacks were observed. The XPS study shows the formation of silicate at the interface of both stacks. The lower surface roughness of 0.15 nm was observed for the LZS gate stack over the ZLS gate stack. This indicates that, La2O3/ZrO2/Si combination could be a more promising candidate for future MOS devices than that of ZrO2/La2O3/Si.
International Journal of Modern Physics B, 2018
The spectroscopic study of La2O3 thin films deposited over Si and SiC at low RF power of 25 W by ... more The spectroscopic study of La2O3 thin films deposited over Si and SiC at low RF power of 25 W by using indigenously developed plasma-enhanced atomic layer deposition (IDPEALD) system has been investigated. The tris (cyclopentadienyl) lanthanum (III) and O2 plasma were used as a source precursor of lanthanum and oxygen, respectively. The [Formula: see text]1.2 nm thick La2O3 over SiC and Si has been formed based on our recipe confirmed by means of cross-sectional transmission electron microscopy. The structural characterization of deposited films was performed by means of X-ray photoelectron Spectroscopy (XPS) and X-ray Diffraction (XRD). The XPS result confirms the formation of 3[Formula: see text] oxidation state of the lanthania. The XRD results reveals that, deposited La2O3 films deposited on SiC are amorphous in nature compare to that of films on Si. The AFM micrograph shows the lowest roughness of 0.26 nm for 30 cycles of La2O3 thin films.
Current Applied Physics, 2021
The HF treatment removes the native oxide and lays behind the dangling bonds over the Si surface ... more The HF treatment removes the native oxide and lays behind the dangling bonds over the Si surface which causes the increment in density of interface traps (D it) through the direct deposition of high-k dielectric on Si. Here, we propose the facile method for reduction of interface traps and improvement in barrier height with the (NH 4) 2 S treatment on Al 2 O 3 /Si interfaces, which can be used as the base for the non-volatile memory device. The AFM was used to optimize the treatment time and surface properties, while XPS measurements were carried out to study the interface and extract the barrier height (Φ B). The short period of 20 s treatment shows the improvement in the barrier height (1.02 eV), while the one order reduction in the D it (0.84 × 10 12 cm 2 /eV) of sulfur passivated Al/Al 2 O 3 /Si MOS device. The results indicate the favorable passivation of the dangling bonds over the Si surfaces covered by sulfur atoms.
Current Applied Physics, 2021
The HF treatment removes the native oxide and lays behind the dangling bonds over the Si surface ... more The HF treatment removes the native oxide and lays behind the dangling bonds over the Si surface which causes the increment in density of interface traps (D it) through the direct deposition of high-k dielectric on Si. Here, we propose the facile method for reduction of interface traps and improvement in barrier height with the (NH 4) 2 S treatment on Al 2 O 3 /Si interfaces, which can be used as the base for the non-volatile memory device. The AFM was used to optimize the treatment time and surface properties, while XPS measurements were carried out to study the interface and extract the barrier height (Φ B). The short period of 20 s treatment shows the improvement in the barrier height (1.02 eV), while the one order reduction in the D it (0.84 × 10 12 cm 2 /eV) of sulfur passivated Al/Al 2 O 3 /Si MOS device. The results indicate the favorable passivation of the dangling bonds over the Si surfaces covered by sulfur atoms.
ECS Journal of Solid State Science and Technology, 2020
Journal of Materials Science: Materials in Electronics, 2020
We report the effect of variation of the channel width-to-length aspect ratio on the negative bia... more We report the effect of variation of the channel width-to-length aspect ratio on the negative bias stress instability and the impact of the source/drain contact resistance on the electrical properties of amorphous-InGaZnO (IGZO) thin-film transistor (TFT) arrays. An asymmetric degradation of the threshold voltage (V th) was observed over a wide range of negative stress bias in the IGZO TFT arrays. The lowest ∆V th of 0.8 V and good stability with an increase in stress time were observed for the array having the channel aspect ratio of ~ 1.5, whereas the highest ∆V th of 5.2 V was observed for the array having the channel aspect ratio of ~ 2.5. The drain-induced barrier lowering (DIBL) mechanism and the transmission line method (TLM) were used to investigate this abnormal degradation. The maximum DIBL of 50.2 mV/V was calculated for the array having a channel width/length of 4.4/11 μm. Application of the TLM revealed a channel resistance of 10.4 kΩ μm at a small gate bias of 0.5 V. Degradation of the electrical properties was observed for the array having an aspect ratio of 2.5 owing to poor ohmic contact with the channel. This investigation suggests that proper selection of the aspect ratio is important in the design of small-scale TFT arrays, as it can help to reduce the degradation of the electrical properties at a smaller dimension. Short-channel effects such as electron trapping and parasitic resistances can be minimized via improvement of the bias stress instability by use of a width-to-length aspect ratio of ~ 1.5. The findings in this report are beneficial for designing ultra-high-definition active-matrix displays.
Solid-State Electronics, 2020
The lower mobility for p-type Ge based is always an issue due to slow traps generation at the int... more The lower mobility for p-type Ge based is always an issue due to slow traps generation at the interface of the metal oxide semiconductor (MOS) device which designates the defects in films generated during the deposition process. One of the effective ways to reduce this slow traps generation is to perform post deposition annealing (PDA) at a certain temperature. However, the selection of proper annealing temperature is the key to reduce defects without damaging the film quality. The effect of different PDA temperatures on the slow traps generation mechanism in the GeON passivated Ge MOS device was examined in this work. The XPS spectra show the stable formation of GeON over Ge, while HRTEM does not show any effect of PDA at the interface of GeON/Ge. The slow trap density (ΔN st) in HfO 2 /GeON/Ge interface annealed at different temperatures was evaluated from the hysteresis curve of C-V sweep as the function of the effective oxide field. The lowest ΔN st (4.01 × 10 12 cm −2) was observed for the PDA temperature for 400 ℃. While, ΔN st increased slightly after PDA at 450 ℃. The work suggests that PDA at lower temperatures is essential to realize the high quality interface with lower interface trap density, enhanced mobility and lower CET in Ge based MOS devices. Further, it also helps to reduce the slow traps generations at the interface.
Semiconductor Science and Technology, 2018
The ZrO2/La2O3 bilayer structure has been formed on Si by using atomic layer deposition system. T... more The ZrO2/La2O3 bilayer structure has been formed on Si by using atomic layer deposition system. The ZrO2/La2O3 (ZLS) bilayer was swapped to La2O3/ZrO2 (LZS) on Si and the interface properties were investigated. The chemical compositions of deposited thin films were studied by using XPS, while surface properties were investigated by means of AFM. The shift in binding energies of both gate stacks were observed. The XPS study shows the formation of silicate at the interface of both stacks. The lower surface roughness of 0.15 nm was observed for the LZS gate stack over the ZLS gate stack. This indicates that, La2O3/ZrO2/Si combination could be a more promising candidate for future MOS devices than that of ZrO2/La2O3/Si.
International Journal of Modern Physics B, 2018
The spectroscopic study of La2O3 thin films deposited over Si and SiC at low RF power of 25 W by ... more The spectroscopic study of La2O3 thin films deposited over Si and SiC at low RF power of 25 W by using indigenously developed plasma-enhanced atomic layer deposition (IDPEALD) system has been investigated. The tris (cyclopentadienyl) lanthanum (III) and O2 plasma were used as a source precursor of lanthanum and oxygen, respectively. The [Formula: see text]1.2 nm thick La2O3 over SiC and Si has been formed based on our recipe confirmed by means of cross-sectional transmission electron microscopy. The structural characterization of deposited films was performed by means of X-ray photoelectron Spectroscopy (XPS) and X-ray Diffraction (XRD). The XPS result confirms the formation of 3[Formula: see text] oxidation state of the lanthania. The XRD results reveals that, deposited La2O3 films deposited on SiC are amorphous in nature compare to that of films on Si. The AFM micrograph shows the lowest roughness of 0.26 nm for 30 cycles of La2O3 thin films.